From patchwork Tue Aug 18 15:50:47 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Taylor Simpson X-Patchwork-Id: 1347115 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=quicinc.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=quicinc.com header.i=@quicinc.com header.a=rsa-sha256 header.s=qcdkim header.b=r+jBqT6d; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4BWFxh5t16z9sTR for ; Wed, 19 Aug 2020 02:00:40 +1000 (AEST) Received: from localhost ([::1]:38792 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1k842Q-0006KC-BE for incoming@patchwork.ozlabs.org; Tue, 18 Aug 2020 12:00:38 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:60862) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1k83tP-0006u1-Vt for qemu-devel@nongnu.org; Tue, 18 Aug 2020 11:51:20 -0400 Received: from alexa-out-sd-01.qualcomm.com ([199.106.114.38]:55154) by eggs.gnu.org with esmtps (TLS1.2:RSA_AES_256_CBC_SHA1:256) (Exim 4.90_1) (envelope-from ) id 1k83tN-0005rj-3H for qemu-devel@nongnu.org; Tue, 18 Aug 2020 11:51:19 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=quicinc.com; i=@quicinc.com; q=dns/txt; s=qcdkim; t=1597765877; x=1629301877; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=3L1TPI1MzRIuwPpVI3GYrWX7dadtEueElJWK+OcmXr4=; b=r+jBqT6d2Grxv+NEzuDW5ldwf4jOSd7efNJbB+I5ACrsa3ORcxyCS+H8 39oIQHwGWfkMo5apSDdz1o2svQQSYb5xgvQZCvj8WaI4Uh+DlDIitjF4o B7zdFNEd3wbD8TrPtFD7ee3GHIwVgYQQIBadmQ7UB1ifCBLge9hfbzCQ0 0=; Received: from unknown (HELO ironmsg05-sd.qualcomm.com) ([10.53.140.145]) by alexa-out-sd-01.qualcomm.com with ESMTP; 18 Aug 2020 08:51:00 -0700 Received: from vu-tsimpson-aus.qualcomm.com (HELO vu-tsimpson1-aus.qualcomm.com) ([10.222.150.1]) by ironmsg05-sd.qualcomm.com with ESMTP; 18 Aug 2020 08:50:59 -0700 Received: by vu-tsimpson1-aus.qualcomm.com (Postfix, from userid 47164) id B1001848; Tue, 18 Aug 2020 10:50:59 -0500 (CDT) From: Taylor Simpson To: qemu-devel@nongnu.org Subject: [RFC PATCH v3 34/34] Hexagon build infrastructure Date: Tue, 18 Aug 2020 10:50:47 -0500 Message-Id: <1597765847-16637-35-git-send-email-tsimpson@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1597765847-16637-1-git-send-email-tsimpson@quicinc.com> References: <1597765847-16637-1-git-send-email-tsimpson@quicinc.com> MIME-Version: 1.0 Received-SPF: pass client-ip=199.106.114.38; envelope-from=tsimpson@qualcomm.com; helo=alexa-out-sd-01.qualcomm.com X-detected-operating-system: by eggs.gnu.org: First seen = 2020/08/18 11:48:34 X-ACL-Warn: Detected OS = FreeBSD 9.x or newer [fuzzy] X-Spam_score_int: -32 X-Spam_score: -3.3 X-Spam_bar: --- X-Spam_report: (-3.3 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, HEADER_FROM_DIFFERENT_DOMAINS=1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: ale@rev.ng, riku.voipio@iki.fi, richard.henderson@linaro.org, laurent@vivier.eu, tsimpson@quicinc.com, philmd@redhat.com, aleksandar.m.mail@gmail.com Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Add file to default-configs Change configure Add target/hexagon/Makefile.objs Change scripts/qemu-binfmt-conf.sh We can build a hexagon-linux-user target and run programs on the Hexagon scalar core. With hexagon-linux-clang installed, "make check-tcg" will pass. Signed-off-by: Taylor Simpson --- configure | 9 ++ default-configs/hexagon-linux-user.mak | 1 + scripts/qemu-binfmt-conf.sh | 6 +- target/hexagon/Makefile.objs | 203 +++++++++++++++++++++++++++++++++ 4 files changed, 218 insertions(+), 1 deletion(-) create mode 100644 default-configs/hexagon-linux-user.mak create mode 100644 target/hexagon/Makefile.objs diff --git a/configure b/configure index 2acc4d1..1f5c5a0 100755 --- a/configure +++ b/configure @@ -8275,6 +8275,12 @@ case "$target_name" in bflt="yes" mttcg="yes" ;; + hexagon) + TARGET_BASE_ARCH=hexagon + TARGET_ABI_DIR=hexagon + mttcg=yes + target_compiler=$cross_cc_hexagon + ;; *) error_exit "Unsupported target CPU" ;; @@ -8447,6 +8453,9 @@ for i in $ARCH $TARGET_BASE_ARCH ; do xtensa*) disas_config "XTENSA" ;; + hexagon) + disas_config "HEXAGON" + ;; esac done if test "$tcg_interpreter" = "yes" ; then diff --git a/default-configs/hexagon-linux-user.mak b/default-configs/hexagon-linux-user.mak new file mode 100644 index 0000000..ad55af0 --- /dev/null +++ b/default-configs/hexagon-linux-user.mak @@ -0,0 +1 @@ +# Default configuration for hexagon-linux-user diff --git a/scripts/qemu-binfmt-conf.sh b/scripts/qemu-binfmt-conf.sh index 9f1580a..7b5d54b 100755 --- a/scripts/qemu-binfmt-conf.sh +++ b/scripts/qemu-binfmt-conf.sh @@ -4,7 +4,7 @@ qemu_target_list="i386 i486 alpha arm armeb sparc sparc32plus sparc64 \ ppc ppc64 ppc64le m68k mips mipsel mipsn32 mipsn32el mips64 mips64el \ sh4 sh4eb s390x aarch64 aarch64_be hppa riscv32 riscv64 xtensa xtensaeb \ -microblaze microblazeel or1k x86_64" +microblaze microblazeel or1k x86_64 hexagon" i386_magic='\x7fELF\x01\x01\x01\x00\x00\x00\x00\x00\x00\x00\x00\x00\x02\x00\x03\x00' i386_mask='\xff\xff\xff\xff\xff\xfe\xfe\x00\xff\xff\xff\xff\xff\xff\xff\xff\xfe\xff\xff\xff' @@ -136,6 +136,10 @@ or1k_magic='\x7fELF\x01\x02\x01\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x02\x00\ or1k_mask='\xff\xff\xff\xff\xff\xff\xff\x00\xff\xff\xff\xff\xff\xff\xff\xff\xff\xfe\xff\xff' or1k_family=or1k +hexagon_magic='\x7fELF\x01\x01\x01\x00\x00\x00\x00\x00\x00\x00\x00\x00\x02\x00\xa4\x00' +hexagon_mask='\xff\xff\xff\xff\xff\xff\xff\x00\xff\xff\xff\xff\xff\xff\xff\xff\xfe\xff\xff\xff' +hexagon_family=hexagon + qemu_get_family() { cpu=${HOST_ARCH:-$(uname -m)} case "$cpu" in diff --git a/target/hexagon/Makefile.objs b/target/hexagon/Makefile.objs new file mode 100644 index 0000000..f9321c8 --- /dev/null +++ b/target/hexagon/Makefile.objs @@ -0,0 +1,203 @@ +## +## Copyright(c) 2019-2020 Qualcomm Innovation Center, Inc. All Rights Reserved. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, see . +## + +obj-y += \ + cpu.o \ + translate.o \ + op_helper.o \ + gdbstub.o \ + genptr.o \ + reg_fields.o \ + decode.o \ + iclass.o \ + opcodes.o \ + printinsn.o \ + arch.o \ + fma_emu.o \ + conv_emu.o + +# +# Step 1 +# We use a C program to create semantics_generated.pyinc +# +BUILD_USER_DIR = $(BUILD_DIR)/hexagon-linux-user +GEN_SEMANTICS = gen_semantics +GEN_SEMANTICS_SRC = $(SRC_PATH)/target/hexagon/gen_semantics.c + +IDEF_FILES = \ + $(SRC_PATH)/target/hexagon/imported/alu.idef \ + $(SRC_PATH)/target/hexagon/imported/branch.idef \ + $(SRC_PATH)/target/hexagon/imported/compare.idef \ + $(SRC_PATH)/target/hexagon/imported/float.idef \ + $(SRC_PATH)/target/hexagon/imported/ldst.idef \ + $(SRC_PATH)/target/hexagon/imported/mpy.idef \ + $(SRC_PATH)/target/hexagon/imported/shift.idef \ + $(SRC_PATH)/target/hexagon/imported/subinsns.idef \ + $(SRC_PATH)/target/hexagon/imported/system.idef +DEF_FILES = \ + $(SRC_PATH)/target/hexagon/imported/allidefs.def \ + $(SRC_PATH)/target/hexagon/imported/macros.def + +$(GEN_SEMANTICS): $(GEN_SEMANTICS_SRC) $(IDEF_FILES) $(DEF_FILES) + $(CC) $(CFLAGS) $(GEN_SEMANTICS_SRC) -o $(GEN_SEMANTICS) + +SEMANTICS=semantics_generated.pyinc +$(SEMANTICS): $(GEN_SEMANTICS) + $(call quiet-command, \ + $(BUILD_USER_DIR)/$(GEN_SEMANTICS) $(SEMANTICS), \ + "GEN", $(SEMANTICS)) + +# +# Step 2 +# We use Python scripts to generate the following files +# +SHORTCODE_H = $(BUILD_USER_DIR)/shortcode_generated.h +HELPER_PROTOS_H = $(BUILD_USER_DIR)/helper_protos_generated.h +TCG_FUNCS_H = $(BUILD_USER_DIR)/tcg_funcs_generated.h +HELPER_FUNCS_H = $(BUILD_USER_DIR)/helper_funcs_generated.h +OPCODES_DEF_H = $(BUILD_USER_DIR)/opcodes_def_generated.h +OP_ATTRIBS_H = $(BUILD_USER_DIR)/op_attribs_generated.h +OP_REGS_H = $(BUILD_USER_DIR)/op_regs_generated.h +PRINTINSN_H = $(BUILD_USER_DIR)/printinsn_generated.h + +GENERATED_HEXAGON_FILES = \ + $(SHORTCODE_H) \ + $(HELPER_PROTOS_H) \ + $(TCG_FUNCS_H) \ + $(HELPER_FUNCS_H) \ + $(OPCODES_DEF_H) \ + $(OP_ATTRIBS_H) \ + $(OP_REGS_H) \ + $(PRINTINSN_H) + +$(SHORTCODE_H): \ + $(SRC_PATH)/target/hexagon/hex_common.py \ + $(SRC_PATH)/target/hexagon/gen_shortcode.py \ + $(SEMANTICS) \ + $(SRC_PATH)/target/hexagon/attribs_def.h + $(call quiet-command, \ + $(SRC_PATH)/target/hexagon/gen_shortcode.py \ + $(SEMANTICS) \ + $(SRC_PATH)/target/hexagon/attribs_def.h, \ + "GEN", "Hexagon shortcode_generated.h") + +$(HELPER_PROTOS_H): \ + $(SRC_PATH)/target/hexagon/hex_common.py \ + $(SRC_PATH)/target/hexagon/gen_helper_protos.py \ + $(SEMANTICS) \ + $(SRC_PATH)/target/hexagon/attribs_def.h + $(call quiet-command, \ + $(SRC_PATH)/target/hexagon/gen_helper_protos.py \ + $(SEMANTICS) \ + $(SRC_PATH)/target/hexagon/attribs_def.h, \ + "GEN", "Hexagon helper_protos_generated.h") + +$(TCG_FUNCS_H): \ + $(SRC_PATH)/target/hexagon/hex_common.py \ + $(SRC_PATH)/target/hexagon/gen_tcg_funcs.py \ + $(SEMANTICS) \ + $(SRC_PATH)/target/hexagon/attribs_def.h + $(call quiet-command, \ + $(SRC_PATH)/target/hexagon/gen_tcg_funcs.py \ + $(SEMANTICS) \ + $(SRC_PATH)/target/hexagon/attribs_def.h, \ + "GEN", "Hexagon tcg_funcs_generated.h") + +$(HELPER_FUNCS_H): \ + $(SRC_PATH)/target/hexagon/hex_common.py \ + $(SRC_PATH)/target/hexagon/gen_helper_funcs.py \ + $(SEMANTICS) \ + $(SRC_PATH)/target/hexagon/attribs_def.h + $(call quiet-command, \ + $(SRC_PATH)/target/hexagon/gen_helper_funcs.py \ + $(SEMANTICS) \ + $(SRC_PATH)/target/hexagon/attribs_def.h, \ + "GEN", "Hexagon helper_funcs_generated.h") + +$(PRINTINSN_H): \ + $(SRC_PATH)/target/hexagon/hex_common.py \ + $(SRC_PATH)/target/hexagon/gen_printinsn.py \ + $(SEMANTICS) \ + $(SRC_PATH)/target/hexagon/attribs_def.h + $(call quiet-command, \ + $(SRC_PATH)/target/hexagon/gen_printinsn.py \ + $(SEMANTICS) \ + $(SRC_PATH)/target/hexagon/attribs_def.h, \ + "GEN", "Hexagon printinsn_generated.h") + +$(OP_REGS_H): \ + $(SRC_PATH)/target/hexagon/hex_common.py \ + $(SRC_PATH)/target/hexagon/gen_op_regs.py \ + $(SEMANTICS) \ + $(SRC_PATH)/target/hexagon/attribs_def.h + $(call quiet-command, \ + $(SRC_PATH)/target/hexagon/gen_op_regs.py \ + $(SEMANTICS) \ + $(SRC_PATH)/target/hexagon/attribs_def.h, \ + "GEN", "Hexagon op_regs_generated.h") + +$(OP_ATTRIBS_H): \ + $(SRC_PATH)/target/hexagon/hex_common.py \ + $(SRC_PATH)/target/hexagon/gen_op_attribs.py \ + $(SEMANTICS) \ + $(SRC_PATH)/target/hexagon/attribs_def.h + $(call quiet-command, \ + $(SRC_PATH)/target/hexagon/gen_op_attribs.py \ + $(SEMANTICS) \ + $(SRC_PATH)/target/hexagon/attribs_def.h, \ + "GEN", "Hexagon op_attribs_generated.h") + +$(OPCODES_DEF_H): \ + $(SRC_PATH)/target/hexagon/hex_common.py \ + $(SRC_PATH)/target/hexagon/gen_opcodes_def.py \ + $(SEMANTICS) \ + $(SRC_PATH)/target/hexagon/attribs_def.h + $(call quiet-command, \ + $(SRC_PATH)/target/hexagon/gen_opcodes_def.py \ + $(SEMANTICS) \ + $(SRC_PATH)/target/hexagon/attribs_def.h, \ + "GEN", "Hexagon opcodes_def_generated.h") + +# +# Step 3 +# We use a C program to create iset.py which is imported into dectree.py +# to create the decode tree +# +GEN_DECTREE_IMPORT=gen_dectree_import +GEN_DECTREE_IMPORT_SRC = $(SRC_PATH)/target/hexagon/gen_dectree_import.c + +$(GEN_DECTREE_IMPORT): $(GEN_DECTREE_IMPORT_SRC) $(OPCODES_DEF_H) config-target.h + $(CC) $(QEMU_CFLAGS) $(QEMU_INCLUDES) -I$(BUILD_DIR) $(GEN_DECTREE_IMPORT_SRC) -o $(GEN_DECTREE_IMPORT) + +DECTREE_IMPORT=iset.py +$(DECTREE_IMPORT): $(GEN_DECTREE_IMPORT) + $(call quiet-command, \ + $(BUILD_USER_DIR)/$(GEN_DECTREE_IMPORT) $(DECTREE_IMPORT), \ + "GEN", $(DECTREE_IMPORT)) + +# +# Step 4 +# We use the dectree.py script to generate the decode tree header file +# +DECTREE_HEADER=dectree_generated.h +$(DECTREE_HEADER): $(SRC_PATH)/target/hexagon/dectree.py $(DECTREE_IMPORT) + $(call quiet-command, \ + PYTHONPATH=$(BUILD_USER_DIR) \ + $(PYTHON) $(SRC_PATH)/target/hexagon/dectree.py, \ + "GEN", "Hexagon decode tree") + +generated-files-y += $(GENERATED_HEXAGON_FILES) $(DECTREE_HEADER)