Message ID | 1597658722-12922-4-git-send-email-bin.meng@windriver.com |
---|---|
State | New |
Headers | show |
Series | hw/sd: Add Cadence SDHCI emulation | expand |
On 8/17/20 12:05 PM, Bin Meng wrote: > Cadence SD/SDIO/eMMC Host Controller (SD4HC) is an SDHCI compatible > controller. The SDHCI compatible registers start from offset 0x200, > which are called Slot Register Set (SRS) in its datasheet. > > This creates a Cadence SDHCI model built on top of the existing > generic SDHCI model. Cadence specific Host Register Set (HRS) is > implemented to make guest software happy. > > Signed-off-by: Bin Meng <bin.meng@windriver.com> > > --- > > Changes in v2: > - use 's' for the model state > - call device_cold_reset() in cadence_sdhci_reset() > - add .impl in cadence_sdhci_ops > - move Cadence specific register defines to cadence_sdhci.c > - use 'sdhci' instead of 'slot' to represent SDHCIState > - use sysbus_mmio_get_region() to access SDHCI model's memory region > - initialize TYPE_SYSBUS_SDHCI in the instance_init() so that users > of Cadence SDHCI do not have to do that themselves > - propergate irq and 'sd-bus' from generic-sdhci > > hw/sd/Kconfig | 4 + > hw/sd/Makefile.objs | 1 + > hw/sd/cadence_sdhci.c | 200 ++++++++++++++++++++++++++++++++++++++++++ > include/hw/sd/cadence_sdhci.h | 46 ++++++++++ > 4 files changed, 251 insertions(+) > create mode 100644 hw/sd/cadence_sdhci.c > create mode 100644 include/hw/sd/cadence_sdhci.h Consider using scripts/git.orderfile ;) > > diff --git a/hw/sd/Kconfig b/hw/sd/Kconfig > index c5e1e55..633b9af 100644 > --- a/hw/sd/Kconfig > +++ b/hw/sd/Kconfig > @@ -19,3 +19,7 @@ config SDHCI_PCI > default y if PCI_DEVICES > depends on PCI > select SDHCI > + > +config CADENCE_SDHCI > + bool > + select SDHCI > diff --git a/hw/sd/Makefile.objs b/hw/sd/Makefile.objs > index 0d1df17..4d500a6 100644 > --- a/hw/sd/Makefile.objs > +++ b/hw/sd/Makefile.objs > @@ -10,3 +10,4 @@ common-obj-$(CONFIG_OMAP) += omap_mmc.o > common-obj-$(CONFIG_PXA2XX) += pxa2xx_mmci.o > common-obj-$(CONFIG_RASPI) += bcm2835_sdhost.o > common-obj-$(CONFIG_ASPEED_SOC) += aspeed_sdhci.o > +common-obj-$(CONFIG_CADENCE_SDHCI) += cadence_sdhci.o > diff --git a/hw/sd/cadence_sdhci.c b/hw/sd/cadence_sdhci.c > new file mode 100644 > index 0000000..4f01d63 > --- /dev/null > +++ b/hw/sd/cadence_sdhci.c > @@ -0,0 +1,200 @@ > +/* > + * Cadence SDHCI emulation > + * > + * Copyright (c) 2020 Wind River Systems, Inc. > + * > + * Author: > + * Bin Meng <bin.meng@windriver.com> > + * > + * This program is free software; you can redistribute it and/or > + * modify it under the terms of the GNU General Public License as > + * published by the Free Software Foundation; either version 2 or > + * (at your option) version 3 of the License. > + * > + * This program is distributed in the hope that it will be useful, > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > + * GNU General Public License for more details. > + * > + * You should have received a copy of the GNU General Public License along > + * with this program; if not, see <http://www.gnu.org/licenses/>. > + */ > + > +#include "qemu/osdep.h" > +#include "qemu/bitops.h" > +#include "qemu/error-report.h" > +#include "qemu/log.h" > +#include "qapi/error.h" > +#include "migration/vmstate.h" > +#include "hw/irq.h" > +#include "hw/sd/cadence_sdhci.h" > +#include "sdhci-internal.h" > + > +/* HRS - Host Register Set (specific to Cadence) */ > + > +#define CADENCE_SDHCI_HRS00 0x00 /* general information */ > +#define CADENCE_SDHCI_HRS00_SWR BIT(0) > +#define CADENCE_SDHCI_HRS00_POR_VAL 0x00010000 > + > +#define CADENCE_SDHCI_HRS04 0x10 /* PHY access port */ > +#define CADENCE_SDHCI_HRS04_WR BIT(24) > +#define CADENCE_SDHCI_HRS04_RD BIT(25) > +#define CADENCE_SDHCI_HRS04_ACK BIT(26) > + > +#define CADENCE_SDHCI_HRS06 0x18 /* eMMC control */ > +#define CADENCE_SDHCI_HRS06_TUNE_UP BIT(15) > + > +/* SRS - Slot Register Set (SDHCI-compatible) */ > + > +#define CADENCE_SDHCI_SRS_BASE 0x200 > + > +#define TO_REG(addr) ((addr) / sizeof(uint32_t)) > + > +static void cadence_sdhci_instance_init(Object *obj) > +{ > + CadenceSDHCIState *s = CADENCE_SDHCI(obj); > + > + object_initialize_child(OBJECT(s), "cadence-sdhci.sdhci", "generic-sdhci"? > + &s->sdhci, TYPE_SYSBUS_SDHCI); > +} > + > +static void cadence_sdhci_reset(DeviceState *dev) > +{ > + CadenceSDHCIState *s = CADENCE_SDHCI(dev); > + > + memset(s->regs, 0, CADENCE_SDHCI_REG_SIZE); > + s->regs[TO_REG(CADENCE_SDHCI_HRS00)] = CADENCE_SDHCI_HRS00_POR_VAL; > + > + device_cold_reset(DEVICE(&s->sdhci)); > +} > + > +static uint64_t cadence_sdhci_read(void *opaque, hwaddr addr, unsigned int size) > +{ > + uint32_t val = 0; > + CadenceSDHCIState *s = opaque; > + > + if (addr < CADENCE_SDHCI_REG_SIZE) { > + val = s->regs[TO_REG(addr)]; > + } else { > + qemu_log_mask(LOG_GUEST_ERROR, > + "%s: Out-of-bounds read at 0x%" HWADDR_PRIx "\n", > + __func__, addr); > + } > + > + return (uint64_t)val; > +} > + > +static void cadence_sdhci_write(void *opaque, hwaddr addr, uint64_t val, > + unsigned int size) > +{ > + CadenceSDHCIState *s = opaque; > + uint32_t val32 = (uint32_t)val; > + > + switch (addr) { > + case CADENCE_SDHCI_HRS00: > + /* > + * The only writable bit is SWR (software reset) and it automatically > + * clears to zero, so essentially this register remains unchanged. > + */ > + if (val32 & CADENCE_SDHCI_HRS00_SWR) { > + cadence_sdhci_reset(DEVICE(s)); > + } > + > + break; > + case CADENCE_SDHCI_HRS04: > + /* > + * Only emulate the ACK bit behavior when read or write transaction > + * are requested. > + */ > + if (val32 & (CADENCE_SDHCI_HRS04_WR | CADENCE_SDHCI_HRS04_RD)) { > + val32 |= CADENCE_SDHCI_HRS04_ACK; > + } else { > + val32 &= ~CADENCE_SDHCI_HRS04_ACK; > + } > + > + s->regs[TO_REG(addr)] = val32; > + break; > + case CADENCE_SDHCI_HRS06: > + if (val32 & CADENCE_SDHCI_HRS06_TUNE_UP) { > + val32 &= ~CADENCE_SDHCI_HRS06_TUNE_UP; > + } > + > + s->regs[TO_REG(addr)] = val32; > + break; > + default: > + if (addr < CADENCE_SDHCI_REG_SIZE) { > + s->regs[TO_REG(addr)] = val32; > + } else { > + qemu_log_mask(LOG_GUEST_ERROR, > + "%s: Out-of-bounds write at 0x%" HWADDR_PRIx "\n", > + __func__, addr); > + } > + } > +} > + > +static const MemoryRegionOps cadence_sdhci_ops = { > + .read = cadence_sdhci_read, > + .write = cadence_sdhci_write, > + .endianness = DEVICE_NATIVE_ENDIAN, > + .impl = { > + .min_access_size = 4, > + .max_access_size = 4, > + }, > + .valid = { > + .min_access_size = 4, > + .max_access_size = 4, > + } > +}; > + > +static void cadence_sdhci_realize(DeviceState *dev, Error **errp) > +{ > + CadenceSDHCIState *s = CADENCE_SDHCI(dev); > + SysBusDevice *sbd = SYS_BUS_DEVICE(dev); > + SysBusDevice *sbd_sdhci = SYS_BUS_DEVICE(&s->sdhci); > + > + memory_region_init_io(&s->iomem, OBJECT(s), &cadence_sdhci_ops, > + s, TYPE_CADENCE_SDHCI, 0x1000); I/O Region of 0x1000 but you only uses 0x100 for the Cadence part and 0x100 for the generic part. Consider creating a container of 0x1000, and map 2 subregions? memory_region_init(&s->container, OBJECT(s), 0x1000); memory_region_init_io(&s->iomem, OBJECT(s), &cadence_sdhci_ops, s, TYPE_CADENCE_SDHCI, CADENCE_SDHCI_REG_SIZE); memory_region_add_subregion(&s->container, 0x000, &s->iomem); You can then simplify your out-of-bounds access checks for cadence_sdhci_ops's read/write. > + sysbus_init_mmio(sbd, &s->iomem); Replace by: sysbus_init_mmio(sbd, &s->container); Using a container seems cleaner, but your patch is fine: Acked-by: Philippe Mathieu-Daudé <f4bug@amsat.org> > + > + sysbus_realize(sbd_sdhci, errp); > + memory_region_add_subregion(&s->iomem, CADENCE_SDHCI_SRS_BASE, > + sysbus_mmio_get_region(sbd_sdhci, 0)); > + > + /* propagate irq and "sd-bus" from generic-sdhci */ > + sysbus_pass_irq(sbd, sbd_sdhci); > + s->bus = qdev_get_child_bus(DEVICE(sbd_sdhci), "sd-bus"); > +} > + > +static const VMStateDescription vmstate_cadence_sdhci = { > + .name = TYPE_CADENCE_SDHCI, > + .version_id = 1, > + .fields = (VMStateField[]) { > + VMSTATE_UINT32_ARRAY(regs, CadenceSDHCIState, CADENCE_SDHCI_NUM_REGS), > + VMSTATE_END_OF_LIST(), > + }, > +}; > + > +static void cadence_sdhci_class_init(ObjectClass *classp, void *data) > +{ > + DeviceClass *dc = DEVICE_CLASS(classp); > + > + dc->desc = "Cadence SD/SDIO/eMMC Host Controller (SD4HC)"; > + dc->realize = cadence_sdhci_realize; > + dc->reset = cadence_sdhci_reset; > + dc->vmsd = &vmstate_cadence_sdhci; > +} > + > +static TypeInfo cadence_sdhci_info = { > + .name = TYPE_CADENCE_SDHCI, > + .parent = TYPE_SYS_BUS_DEVICE, > + .instance_size = sizeof(CadenceSDHCIState), > + .instance_init = cadence_sdhci_instance_init, > + .class_init = cadence_sdhci_class_init, > +}; > + > +static void cadence_sdhci_register_types(void) > +{ > + type_register_static(&cadence_sdhci_info); > +} > + > +type_init(cadence_sdhci_register_types) > diff --git a/include/hw/sd/cadence_sdhci.h b/include/hw/sd/cadence_sdhci.h > new file mode 100644 > index 0000000..9b52115 > --- /dev/null > +++ b/include/hw/sd/cadence_sdhci.h > @@ -0,0 +1,46 @@ > +/* > + * Cadence SDHCI emulation > + * > + * Copyright (c) 2020 Wind River Systems, Inc. > + * > + * Author: > + * Bin Meng <bin.meng@windriver.com> > + * > + * This program is free software; you can redistribute it and/or > + * modify it under the terms of the GNU General Public License as > + * published by the Free Software Foundation; either version 2 or > + * (at your option) version 3 of the License. > + * > + * This program is distributed in the hope that it will be useful, > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > + * GNU General Public License for more details. > + * > + * You should have received a copy of the GNU General Public License along > + * with this program; if not, see <http://www.gnu.org/licenses/>. > + */ > + > +#ifndef CADENCE_SDHCI_H > +#define CADENCE_SDHCI_H > + > +#include "hw/sd/sdhci.h" > + > +#define CADENCE_SDHCI_REG_SIZE 0x100 > +#define CADENCE_SDHCI_NUM_REGS (CADENCE_SDHCI_REG_SIZE / sizeof(uint32_t)) > + > +typedef struct CadenceSDHCIState { > + SysBusDevice parent; > + > + MemoryRegion iomem; > + BusState *bus; > + > + uint32_t regs[CADENCE_SDHCI_NUM_REGS]; > + > + SDHCIState sdhci; > +} CadenceSDHCIState; > + > +#define TYPE_CADENCE_SDHCI "cadence.sdhci" > +#define CADENCE_SDHCI(obj) OBJECT_CHECK(CadenceSDHCIState, (obj), \ > + TYPE_CADENCE_SDHCI) > + > +#endif /* CADENCE_SDHCI_H */ >
diff --git a/hw/sd/Kconfig b/hw/sd/Kconfig index c5e1e55..633b9af 100644 --- a/hw/sd/Kconfig +++ b/hw/sd/Kconfig @@ -19,3 +19,7 @@ config SDHCI_PCI default y if PCI_DEVICES depends on PCI select SDHCI + +config CADENCE_SDHCI + bool + select SDHCI diff --git a/hw/sd/Makefile.objs b/hw/sd/Makefile.objs index 0d1df17..4d500a6 100644 --- a/hw/sd/Makefile.objs +++ b/hw/sd/Makefile.objs @@ -10,3 +10,4 @@ common-obj-$(CONFIG_OMAP) += omap_mmc.o common-obj-$(CONFIG_PXA2XX) += pxa2xx_mmci.o common-obj-$(CONFIG_RASPI) += bcm2835_sdhost.o common-obj-$(CONFIG_ASPEED_SOC) += aspeed_sdhci.o +common-obj-$(CONFIG_CADENCE_SDHCI) += cadence_sdhci.o diff --git a/hw/sd/cadence_sdhci.c b/hw/sd/cadence_sdhci.c new file mode 100644 index 0000000..4f01d63 --- /dev/null +++ b/hw/sd/cadence_sdhci.c @@ -0,0 +1,200 @@ +/* + * Cadence SDHCI emulation + * + * Copyright (c) 2020 Wind River Systems, Inc. + * + * Author: + * Bin Meng <bin.meng@windriver.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 or + * (at your option) version 3 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see <http://www.gnu.org/licenses/>. + */ + +#include "qemu/osdep.h" +#include "qemu/bitops.h" +#include "qemu/error-report.h" +#include "qemu/log.h" +#include "qapi/error.h" +#include "migration/vmstate.h" +#include "hw/irq.h" +#include "hw/sd/cadence_sdhci.h" +#include "sdhci-internal.h" + +/* HRS - Host Register Set (specific to Cadence) */ + +#define CADENCE_SDHCI_HRS00 0x00 /* general information */ +#define CADENCE_SDHCI_HRS00_SWR BIT(0) +#define CADENCE_SDHCI_HRS00_POR_VAL 0x00010000 + +#define CADENCE_SDHCI_HRS04 0x10 /* PHY access port */ +#define CADENCE_SDHCI_HRS04_WR BIT(24) +#define CADENCE_SDHCI_HRS04_RD BIT(25) +#define CADENCE_SDHCI_HRS04_ACK BIT(26) + +#define CADENCE_SDHCI_HRS06 0x18 /* eMMC control */ +#define CADENCE_SDHCI_HRS06_TUNE_UP BIT(15) + +/* SRS - Slot Register Set (SDHCI-compatible) */ + +#define CADENCE_SDHCI_SRS_BASE 0x200 + +#define TO_REG(addr) ((addr) / sizeof(uint32_t)) + +static void cadence_sdhci_instance_init(Object *obj) +{ + CadenceSDHCIState *s = CADENCE_SDHCI(obj); + + object_initialize_child(OBJECT(s), "cadence-sdhci.sdhci", + &s->sdhci, TYPE_SYSBUS_SDHCI); +} + +static void cadence_sdhci_reset(DeviceState *dev) +{ + CadenceSDHCIState *s = CADENCE_SDHCI(dev); + + memset(s->regs, 0, CADENCE_SDHCI_REG_SIZE); + s->regs[TO_REG(CADENCE_SDHCI_HRS00)] = CADENCE_SDHCI_HRS00_POR_VAL; + + device_cold_reset(DEVICE(&s->sdhci)); +} + +static uint64_t cadence_sdhci_read(void *opaque, hwaddr addr, unsigned int size) +{ + uint32_t val = 0; + CadenceSDHCIState *s = opaque; + + if (addr < CADENCE_SDHCI_REG_SIZE) { + val = s->regs[TO_REG(addr)]; + } else { + qemu_log_mask(LOG_GUEST_ERROR, + "%s: Out-of-bounds read at 0x%" HWADDR_PRIx "\n", + __func__, addr); + } + + return (uint64_t)val; +} + +static void cadence_sdhci_write(void *opaque, hwaddr addr, uint64_t val, + unsigned int size) +{ + CadenceSDHCIState *s = opaque; + uint32_t val32 = (uint32_t)val; + + switch (addr) { + case CADENCE_SDHCI_HRS00: + /* + * The only writable bit is SWR (software reset) and it automatically + * clears to zero, so essentially this register remains unchanged. + */ + if (val32 & CADENCE_SDHCI_HRS00_SWR) { + cadence_sdhci_reset(DEVICE(s)); + } + + break; + case CADENCE_SDHCI_HRS04: + /* + * Only emulate the ACK bit behavior when read or write transaction + * are requested. + */ + if (val32 & (CADENCE_SDHCI_HRS04_WR | CADENCE_SDHCI_HRS04_RD)) { + val32 |= CADENCE_SDHCI_HRS04_ACK; + } else { + val32 &= ~CADENCE_SDHCI_HRS04_ACK; + } + + s->regs[TO_REG(addr)] = val32; + break; + case CADENCE_SDHCI_HRS06: + if (val32 & CADENCE_SDHCI_HRS06_TUNE_UP) { + val32 &= ~CADENCE_SDHCI_HRS06_TUNE_UP; + } + + s->regs[TO_REG(addr)] = val32; + break; + default: + if (addr < CADENCE_SDHCI_REG_SIZE) { + s->regs[TO_REG(addr)] = val32; + } else { + qemu_log_mask(LOG_GUEST_ERROR, + "%s: Out-of-bounds write at 0x%" HWADDR_PRIx "\n", + __func__, addr); + } + } +} + +static const MemoryRegionOps cadence_sdhci_ops = { + .read = cadence_sdhci_read, + .write = cadence_sdhci_write, + .endianness = DEVICE_NATIVE_ENDIAN, + .impl = { + .min_access_size = 4, + .max_access_size = 4, + }, + .valid = { + .min_access_size = 4, + .max_access_size = 4, + } +}; + +static void cadence_sdhci_realize(DeviceState *dev, Error **errp) +{ + CadenceSDHCIState *s = CADENCE_SDHCI(dev); + SysBusDevice *sbd = SYS_BUS_DEVICE(dev); + SysBusDevice *sbd_sdhci = SYS_BUS_DEVICE(&s->sdhci); + + memory_region_init_io(&s->iomem, OBJECT(s), &cadence_sdhci_ops, + s, TYPE_CADENCE_SDHCI, 0x1000); + sysbus_init_mmio(sbd, &s->iomem); + + sysbus_realize(sbd_sdhci, errp); + memory_region_add_subregion(&s->iomem, CADENCE_SDHCI_SRS_BASE, + sysbus_mmio_get_region(sbd_sdhci, 0)); + + /* propagate irq and "sd-bus" from generic-sdhci */ + sysbus_pass_irq(sbd, sbd_sdhci); + s->bus = qdev_get_child_bus(DEVICE(sbd_sdhci), "sd-bus"); +} + +static const VMStateDescription vmstate_cadence_sdhci = { + .name = TYPE_CADENCE_SDHCI, + .version_id = 1, + .fields = (VMStateField[]) { + VMSTATE_UINT32_ARRAY(regs, CadenceSDHCIState, CADENCE_SDHCI_NUM_REGS), + VMSTATE_END_OF_LIST(), + }, +}; + +static void cadence_sdhci_class_init(ObjectClass *classp, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(classp); + + dc->desc = "Cadence SD/SDIO/eMMC Host Controller (SD4HC)"; + dc->realize = cadence_sdhci_realize; + dc->reset = cadence_sdhci_reset; + dc->vmsd = &vmstate_cadence_sdhci; +} + +static TypeInfo cadence_sdhci_info = { + .name = TYPE_CADENCE_SDHCI, + .parent = TYPE_SYS_BUS_DEVICE, + .instance_size = sizeof(CadenceSDHCIState), + .instance_init = cadence_sdhci_instance_init, + .class_init = cadence_sdhci_class_init, +}; + +static void cadence_sdhci_register_types(void) +{ + type_register_static(&cadence_sdhci_info); +} + +type_init(cadence_sdhci_register_types) diff --git a/include/hw/sd/cadence_sdhci.h b/include/hw/sd/cadence_sdhci.h new file mode 100644 index 0000000..9b52115 --- /dev/null +++ b/include/hw/sd/cadence_sdhci.h @@ -0,0 +1,46 @@ +/* + * Cadence SDHCI emulation + * + * Copyright (c) 2020 Wind River Systems, Inc. + * + * Author: + * Bin Meng <bin.meng@windriver.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 or + * (at your option) version 3 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see <http://www.gnu.org/licenses/>. + */ + +#ifndef CADENCE_SDHCI_H +#define CADENCE_SDHCI_H + +#include "hw/sd/sdhci.h" + +#define CADENCE_SDHCI_REG_SIZE 0x100 +#define CADENCE_SDHCI_NUM_REGS (CADENCE_SDHCI_REG_SIZE / sizeof(uint32_t)) + +typedef struct CadenceSDHCIState { + SysBusDevice parent; + + MemoryRegion iomem; + BusState *bus; + + uint32_t regs[CADENCE_SDHCI_NUM_REGS]; + + SDHCIState sdhci; +} CadenceSDHCIState; + +#define TYPE_CADENCE_SDHCI "cadence.sdhci" +#define CADENCE_SDHCI(obj) OBJECT_CHECK(CadenceSDHCIState, (obj), \ + TYPE_CADENCE_SDHCI) + +#endif /* CADENCE_SDHCI_H */
Cadence SD/SDIO/eMMC Host Controller (SD4HC) is an SDHCI compatible controller. The SDHCI compatible registers start from offset 0x200, which are called Slot Register Set (SRS) in its datasheet. This creates a Cadence SDHCI model built on top of the existing generic SDHCI model. Cadence specific Host Register Set (HRS) is implemented to make guest software happy. Signed-off-by: Bin Meng <bin.meng@windriver.com> --- Changes in v2: - use 's' for the model state - call device_cold_reset() in cadence_sdhci_reset() - add .impl in cadence_sdhci_ops - move Cadence specific register defines to cadence_sdhci.c - use 'sdhci' instead of 'slot' to represent SDHCIState - use sysbus_mmio_get_region() to access SDHCI model's memory region - initialize TYPE_SYSBUS_SDHCI in the instance_init() so that users of Cadence SDHCI do not have to do that themselves - propergate irq and 'sd-bus' from generic-sdhci hw/sd/Kconfig | 4 + hw/sd/Makefile.objs | 1 + hw/sd/cadence_sdhci.c | 200 ++++++++++++++++++++++++++++++++++++++++++ include/hw/sd/cadence_sdhci.h | 46 ++++++++++ 4 files changed, 251 insertions(+) create mode 100644 hw/sd/cadence_sdhci.c create mode 100644 include/hw/sd/cadence_sdhci.h