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[18/18] hw/riscv: microchip_pfsoc: Document the software used for testing

Message ID 1597423256-14847-19-git-send-email-bmeng.cn@gmail.com
State Superseded
Headers show
Series hw/riscv: Add Microchip PolarFire SoC Icicle Kit board support | expand

Commit Message

Bin Meng Aug. 14, 2020, 4:40 p.m. UTC 
From: Bin Meng <bin.meng@windriver.com>

Add some useful comments to document the software used for testing.
including how to patch HSS to bypass the DDR memory initialization,
HSS and Yocto BSP build instructions, etc.

To launch this machine for testing:
$ qemu-system-riscv64 -M microchip-icicle-kit -smp 5 \
    -bios path/to/hss.bin -sd path/to/sdcard.img \
    -nic user,model=cadence_gem \
    -nic tap,ifname=tap,model=cadence_gem \
    -display none -serial stdio \
    -chardev socket,id=serial1,path=serial1.sock,server,wait \
    -serial chardev:serial1

Signed-off-by: Bin Meng <bin.meng@windriver.com>

---

 hw/riscv/microchip_pfsoc.c | 21 +++++++++++++++++++++
 1 file changed, 21 insertions(+)

Comments

Alistair Francis Aug. 21, 2020, 6:51 p.m. UTC | #1 
On Fri, Aug 14, 2020 at 9:49 AM Bin Meng <bmeng.cn@gmail.com> wrote:
>
> From: Bin Meng <bin.meng@windriver.com>
>
> Add some useful comments to document the software used for testing.
> including how to patch HSS to bypass the DDR memory initialization,
> HSS and Yocto BSP build instructions, etc.
>
> To launch this machine for testing:
> $ qemu-system-riscv64 -M microchip-icicle-kit -smp 5 \
>     -bios path/to/hss.bin -sd path/to/sdcard.img \
>     -nic user,model=cadence_gem \
>     -nic tap,ifname=tap,model=cadence_gem \
>     -display none -serial stdio \
>     -chardev socket,id=serial1,path=serial1.sock,server,wait \
>     -serial chardev:serial1
>
> Signed-off-by: Bin Meng <bin.meng@windriver.com>
>
> ---
>
>  hw/riscv/microchip_pfsoc.c | 21 +++++++++++++++++++++
>  1 file changed, 21 insertions(+)
>
> diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c
> index e8b7f86..1575fef 100644
> --- a/hw/riscv/microchip_pfsoc.c
> +++ b/hw/riscv/microchip_pfsoc.c
> @@ -56,6 +56,27 @@
>  /*
>   * The BIOS image used by this machine is called Hart Software Services (HSS).
>   * See https://github.com/polarfire-soc/hart-software-services
> + *
> + * As of now the DDR memory controller in the Microchip PolarFire SoC has not
> + * been modeled. Simply creating unimplemented devices does not make HSS happy.
> + * Emulating the DDR memory controller is tedious, so a patched HSS should be
> + * used as the BIOS for this machine.
> + *
> + * To patch HSS, open boards/icicle-kit-es/hss_board_init.c in the HSS source
> + * tree, find the boardInitFunctions[] array that contains the initialization
> + * routines for this board, and remove the line that contains 'HSS_DDRInit'.
> + *
> + * QEMU does not support eMMC hence the SD configuration shall be used in the
> + * HSS and Yocto BSP build. The eMMC configuration is not supported.
> + *
> + * Instructions to build HSS:
> + *   $ cp boards/icicle-kit-es/def_config.sdcard .config
> + *   $ make BOARD=icicle-kit-es
> + *
> + * For Yocto build, "MACHINE=icicle-kit-es-sd" should be specified, otherwise
> + * when booting Linux kernel the rootfs cannot be mounted. The generated image
> + * is something like: mpfs-dev-cli-icicle-kit-es-sd.rootfs.wic. Resize the file
> + * with 'qemu-image' to a power of 2 before passing to QEMU '-sd' command line.

Instead of adding comments in the code (where it's hard for users to
find and prone to getting out of date) can you drop this patch and
instead update the RISC-V QEMU wiki?

https://wiki.qemu.org/Documentation/Platforms/RISCV

Just add an Icicle section.

Alistair

>   */
>  #define BIOS_FILENAME   "hss.bin"
>  #define RESET_VECTOR    0x20220000
> --
> 2.7.4
>
>
diff mbox series

Patch

diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c
index e8b7f86..1575fef 100644
--- a/hw/riscv/microchip_pfsoc.c
+++ b/hw/riscv/microchip_pfsoc.c
@@ -56,6 +56,27 @@ 
 /*
  * The BIOS image used by this machine is called Hart Software Services (HSS).
  * See https://github.com/polarfire-soc/hart-software-services
+ *
+ * As of now the DDR memory controller in the Microchip PolarFire SoC has not
+ * been modeled. Simply creating unimplemented devices does not make HSS happy.
+ * Emulating the DDR memory controller is tedious, so a patched HSS should be
+ * used as the BIOS for this machine.
+ *
+ * To patch HSS, open boards/icicle-kit-es/hss_board_init.c in the HSS source
+ * tree, find the boardInitFunctions[] array that contains the initialization
+ * routines for this board, and remove the line that contains 'HSS_DDRInit'.
+ *
+ * QEMU does not support eMMC hence the SD configuration shall be used in the
+ * HSS and Yocto BSP build. The eMMC configuration is not supported.
+ *
+ * Instructions to build HSS:
+ *   $ cp boards/icicle-kit-es/def_config.sdcard .config
+ *   $ make BOARD=icicle-kit-es
+ *
+ * For Yocto build, "MACHINE=icicle-kit-es-sd" should be specified, otherwise
+ * when booting Linux kernel the rootfs cannot be mounted. The generated image
+ * is something like: mpfs-dev-cli-icicle-kit-es-sd.rootfs.wic. Resize the file
+ * with 'qemu-image' to a power of 2 before passing to QEMU '-sd' command line.
  */
 #define BIOS_FILENAME   "hss.bin"
 #define RESET_VECTOR    0x20220000