From patchwork Tue Aug 4 19:00:27 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Julien Freche <1879587@bugs.launchpad.net> X-Patchwork-Id: 1340986 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=bugs.launchpad.net Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4BLkkS5R8Jz9sR4 for ; Wed, 5 Aug 2020 05:06:23 +1000 (AEST) Received: from localhost ([::1]:35326 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1k32GS-00068r-1r for incoming@patchwork.ozlabs.org; Tue, 04 Aug 2020 15:06:20 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:36242) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1k32GA-00068W-So for qemu-devel@nongnu.org; Tue, 04 Aug 2020 15:06:02 -0400 Received: from indium.canonical.com ([91.189.90.7]:41496) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1k32G8-0004Jg-P1 for qemu-devel@nongnu.org; Tue, 04 Aug 2020 15:06:02 -0400 Received: from loganberry.canonical.com ([91.189.90.37]) by indium.canonical.com with esmtp (Exim 4.86_2 #2 (Debian)) id 1k32G5-0001Uq-MN for ; Tue, 04 Aug 2020 19:05:57 +0000 Received: from loganberry.canonical.com (localhost [127.0.0.1]) by loganberry.canonical.com (Postfix) with ESMTP id 9E0622E8109 for ; Tue, 4 Aug 2020 19:05:57 +0000 (UTC) MIME-Version: 1.0 Date: Tue, 04 Aug 2020 19:00:27 -0000 From: Julien Freche <1879587@bugs.launchpad.net> To: qemu-devel@nongnu.org X-Launchpad-Notification-Type: bug X-Launchpad-Bug: product=qemu; status=In Progress; importance=Undecided; assignee=None; X-Launchpad-Bug-Tags: arm X-Launchpad-Bug-Information-Type: Public X-Launchpad-Bug-Private: no X-Launchpad-Bug-Security-Vulnerability: no X-Launchpad-Bug-Commenters: jfreche pmaydell X-Launchpad-Bug-Reporter: Julien Freche (jfreche) X-Launchpad-Bug-Modifier: Julien Freche (jfreche) References: <158993429952.22373.5947926664408541430.malonedeb@wampee.canonical.com> Message-Id: <159656762727.3307.10681427266283405211.malone@gac.canonical.com> Subject: [Bug 1879587] Re: Register number in ESR is incorrect for certain banked registers when switching from AA32 to AA64 X-Launchpad-Message-Rationale: Subscriber (QEMU) @qemu-devel-ml X-Launchpad-Message-For: qemu-devel-ml Precedence: bulk X-Generated-By: Launchpad (canonical.com); Revision="a24057fea7e4c6a98c0220d5f878da0f3c783699"; Instance="production-secrets-lazr.conf" X-Launchpad-Hash: 479a02cd1917b8bfa5d7efe15e5c68ab8c19aef8 Received-SPF: none client-ip=91.189.90.7; envelope-from=bounces@canonical.com; helo=indium.canonical.com X-detected-operating-system: by eggs.gnu.org: First seen = 2020/08/04 15:05:58 X-ACL-Warn: Detected OS = Linux 3.11 and newer [fuzzy] X-Spam_score_int: -58 X-Spam_score: -5.9 X-Spam_bar: ----- X-Spam_report: (-5.9 / 5.0 requ) BAYES_00=-1.9, HEADER_FROM_DIFFERENT_DOMAINS=1, RCVD_IN_DNSWL_HI=-5, RCVD_IN_MSPIKE_H3=-0.01, RCVD_IN_MSPIKE_WL=-0.01, SPF_HELO_NONE=0.001, SPF_NONE=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-To: Bug 1879587 <1879587@bugs.launchpad.net> Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Unfortunately, I won't be able to send the code or binary for the hypervisor as of now (it will become available at some point in the future though). I've done a bit of debugging on the QEMU code and it seems like the approach you are taking works fine in general but the register mapping code doesn't seem quite right. Applying this patch (on top of yours): >From e2182581dcdeedc2cb88cd21b88b4db744677737 Mon Sep 17 00:00:00 2001 From: Julien Freche Date: Tue, 4 Aug 2020 11:54:49 -0700 Subject: [PATCH] Possible fix --- target/arm/helper.c | 11 +++++------ 1 file changed, 5 insertions(+), 6 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 60b80228fd..455c92b891 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -9619,17 +9619,16 @@ static int aarch64_regnum(CPUARMState *env, int aarch32_reg) switch (mode) { case ARM_CPU_MODE_USR: case ARM_CPU_MODE_SYS: - return 14; case ARM_CPU_MODE_HYP: - return 16; + return 14; case ARM_CPU_MODE_IRQ: - return 18; + return 16; case ARM_CPU_MODE_SVC: - return 20; + return 18; case ARM_CPU_MODE_ABT: - return 22; + return 20; case ARM_CPU_MODE_UND: - return 24; + return 22; case ARM_CPU_MODE_FIQ: return 30; default: