diff mbox series

[Bug,1879587] Re: Register number in ESR is incorrect for certain banked registers when switching from AA32 to AA64

Message ID 159656762727.3307.10681427266283405211.malone@gac.canonical.com
State New
Headers show
Series [Bug,1879587] Re: Register number in ESR is incorrect for certain banked registers when switching from AA32 to AA64 | expand

Commit Message

Julien Freche Aug. 4, 2020, 7 p.m. UTC
Unfortunately, I won't be able to send the code or binary for the
hypervisor as of now (it will become available at some point in the
future though). I've done a bit of debugging on the QEMU code and it
seems like the approach you are taking works fine in general but the
register mapping code doesn't seem quite right. Applying this patch (on
top of yours):

>From e2182581dcdeedc2cb88cd21b88b4db744677737 Mon Sep 17 00:00:00 2001
From: Julien Freche <julien@bedrocksystems.com>
Date: Tue, 4 Aug 2020 11:54:49 -0700
Subject: [PATCH] Possible fix

---
 target/arm/helper.c | 11 +++++------
 1 file changed, 5 insertions(+), 6 deletions(-)
diff mbox series

Patch

diff --git a/target/arm/helper.c b/target/arm/helper.c
index 60b80228fd..455c92b891 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -9619,17 +9619,16 @@  static int aarch64_regnum(CPUARMState *env, int aarch32_reg)
         switch (mode) {
         case ARM_CPU_MODE_USR:
         case ARM_CPU_MODE_SYS:
-            return 14;
         case ARM_CPU_MODE_HYP:
-            return 16;
+            return 14;
         case ARM_CPU_MODE_IRQ:
-            return 18;
+            return 16;
         case ARM_CPU_MODE_SVC:
-            return 20;
+            return 18;
         case ARM_CPU_MODE_ABT:
-            return 22;
+            return 20;
         case ARM_CPU_MODE_UND:
-            return 24;
+            return 22;
         case ARM_CPU_MODE_FIQ:
             return 30;
         default: