From patchwork Sun Aug 20 17:23:05 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: BALATON Zoltan X-Patchwork-Id: 803766 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=2001:4830:134:3::11; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3xb48F4c59z9s7C for ; Mon, 21 Aug 2017 03:49:30 +1000 (AEST) Received: from localhost ([::1]:42998 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1djULo-0004Bh-Kb for incoming@patchwork.ozlabs.org; Sun, 20 Aug 2017 13:49:28 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:39805) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1djUKy-000456-HB for qemu-devel@nongnu.org; Sun, 20 Aug 2017 13:48:39 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1djUKv-00053t-J3 for qemu-devel@nongnu.org; Sun, 20 Aug 2017 13:48:36 -0400 Received: from zero.eik.bme.hu ([152.66.115.2]:27117) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1djUKv-00052g-5Z; Sun, 20 Aug 2017 13:48:33 -0400 Received: from zero.eik.bme.hu (blah.eik.bme.hu [152.66.115.182]) by localhost (Postfix) with SMTP id A6B54747DDC; Sun, 20 Aug 2017 19:48:31 +0200 (CEST) Received: by zero.eik.bme.hu (Postfix, from userid 432) id 14A04747BD3; Sun, 20 Aug 2017 19:48:31 +0200 (CEST) Message-Id: <158c09e2f3e7930786edcc49bcd9b19b9f92bfa5.1503249785.git.balaton@eik.bme.hu> In-Reply-To: References: From: BALATON Zoltan Date: Sun, 20 Aug 2017 19:23:05 +0200 To: qemu-devel@nongnu.org, qemu-ppc@nongnu.org X-detected-operating-system: by eggs.gnu.org: FreeBSD 9.x [fuzzy] X-Received-From: 152.66.115.2 Subject: [Qemu-devel] [PATCH 02/15] ppc4xx: Make MAL emulation more generic X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Francois Revol , Alexander Graf , David Gibson Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Allow MAL with more RX and TX channels as found in newer versions. Signed-off-by: BALATON Zoltan Reviewed-by: David Gibson --- hw/ppc/ppc405_uc.c | 2 +- hw/ppc/ppc4xx_devs.c | 171 +++++++++++++++++++----------------------------- include/hw/ppc/ppc4xx.h | 3 +- 3 files changed, 70 insertions(+), 106 deletions(-) diff --git a/hw/ppc/ppc405_uc.c b/hw/ppc/ppc405_uc.c index 3c74402..03856d5 100644 --- a/hw/ppc/ppc405_uc.c +++ b/hw/ppc/ppc405_uc.c @@ -2281,7 +2281,7 @@ CPUPPCState *ppc405ep_init(MemoryRegion *address_space_mem, mal_irqs[1] = pic[12]; mal_irqs[2] = pic[13]; mal_irqs[3] = pic[14]; - ppc405_mal_init(env, mal_irqs); + ppc4xx_mal_init(env, 4, 2, mal_irqs); /* Ethernet */ /* Uses pic[9], pic[15], pic[17] */ /* CPU control */ diff --git a/hw/ppc/ppc4xx_devs.c b/hw/ppc/ppc4xx_devs.c index 8e4f78e..6e1cc09 100644 --- a/hw/ppc/ppc4xx_devs.c +++ b/hw/ppc/ppc4xx_devs.c @@ -737,6 +737,7 @@ ram_addr_t ppc4xx_sdram_adjust(ram_addr_t ram_size, int nr_banks, /*****************************************************************************/ /* MAL */ + enum { MAL0_CFG = 0x180, MAL0_ESR = 0x181, @@ -750,17 +751,13 @@ enum { MAL0_RXEOBISR = 0x192, MAL0_RXDEIR = 0x193, MAL0_TXCTP0R = 0x1A0, - MAL0_TXCTP1R = 0x1A1, - MAL0_TXCTP2R = 0x1A2, - MAL0_TXCTP3R = 0x1A3, MAL0_RXCTP0R = 0x1C0, - MAL0_RXCTP1R = 0x1C1, MAL0_RCBS0 = 0x1E0, MAL0_RCBS1 = 0x1E1, }; -typedef struct ppc40x_mal_t ppc40x_mal_t; -struct ppc40x_mal_t { +typedef struct ppc4xx_mal_t ppc4xx_mal_t; +struct ppc4xx_mal_t { qemu_irq irqs[4]; uint32_t cfg; uint32_t esr; @@ -773,16 +770,32 @@ struct ppc40x_mal_t { uint32_t rxcarr; uint32_t rxeobisr; uint32_t rxdeir; - uint32_t txctpr[4]; - uint32_t rxctpr[2]; - uint32_t rcbs[2]; + uint32_t *txctpr; + uint32_t *rxctpr; + uint32_t *rcbs; + uint8_t txcnum; + uint8_t rxcnum; }; -static void ppc40x_mal_reset(void *opaque); +static void ppc4xx_mal_reset(void *opaque) +{ + ppc4xx_mal_t *mal; + + mal = opaque; + mal->cfg = 0x0007C000; + mal->esr = 0x00000000; + mal->ier = 0x00000000; + mal->rxcasr = 0x00000000; + mal->rxdeir = 0x00000000; + mal->rxeobisr = 0x00000000; + mal->txcasr = 0x00000000; + mal->txdeir = 0x00000000; + mal->txeobisr = 0x00000000; +} static uint32_t dcr_read_mal(void *opaque, int dcrn) { - ppc40x_mal_t *mal; + ppc4xx_mal_t *mal; uint32_t ret; mal = opaque; @@ -820,48 +833,32 @@ static uint32_t dcr_read_mal(void *opaque, int dcrn) case MAL0_RXDEIR: ret = mal->rxdeir; break; - case MAL0_TXCTP0R: - ret = mal->txctpr[0]; - break; - case MAL0_TXCTP1R: - ret = mal->txctpr[1]; - break; - case MAL0_TXCTP2R: - ret = mal->txctpr[2]; - break; - case MAL0_TXCTP3R: - ret = mal->txctpr[3]; - break; - case MAL0_RXCTP0R: - ret = mal->rxctpr[0]; - break; - case MAL0_RXCTP1R: - ret = mal->rxctpr[1]; - break; - case MAL0_RCBS0: - ret = mal->rcbs[0]; - break; - case MAL0_RCBS1: - ret = mal->rcbs[1]; - break; default: ret = 0; break; } + if (dcrn >= MAL0_TXCTP0R && dcrn < MAL0_TXCTP0R + mal->txcnum) { + ret = mal->txctpr[dcrn - MAL0_TXCTP0R]; + } + if (dcrn >= MAL0_RXCTP0R && dcrn < MAL0_RXCTP0R + mal->rxcnum) { + ret = mal->rxctpr[dcrn - MAL0_RXCTP0R]; + } + if (dcrn >= MAL0_RCBS0 && dcrn < MAL0_RCBS0 + mal->rxcnum) { + ret = mal->rcbs[dcrn - MAL0_RCBS0]; + } return ret; } static void dcr_write_mal(void *opaque, int dcrn, uint32_t val) { - ppc40x_mal_t *mal; - int idx; + ppc4xx_mal_t *mal; mal = opaque; switch (dcrn) { case MAL0_CFG: if (val & 0x80000000) { - ppc40x_mal_reset(mal); + ppc4xx_mal_reset(mal); } mal->cfg = val & 0x00FFC087; break; @@ -900,65 +897,35 @@ static void dcr_write_mal(void *opaque, int dcrn, uint32_t val) /* Read/clear */ mal->rxdeir &= ~val; break; - case MAL0_TXCTP0R: - idx = 0; - goto update_tx_ptr; - case MAL0_TXCTP1R: - idx = 1; - goto update_tx_ptr; - case MAL0_TXCTP2R: - idx = 2; - goto update_tx_ptr; - case MAL0_TXCTP3R: - idx = 3; - update_tx_ptr: - mal->txctpr[idx] = val; - break; - case MAL0_RXCTP0R: - idx = 0; - goto update_rx_ptr; - case MAL0_RXCTP1R: - idx = 1; - update_rx_ptr: - mal->rxctpr[idx] = val; - break; - case MAL0_RCBS0: - idx = 0; - goto update_rx_size; - case MAL0_RCBS1: - idx = 1; - update_rx_size: - mal->rcbs[idx] = val & 0x000000FF; - break; + } + if (dcrn >= MAL0_TXCTP0R && dcrn < MAL0_TXCTP0R + mal->txcnum) { + mal->txctpr[dcrn - MAL0_TXCTP0R] = val; + } + if (dcrn >= MAL0_RXCTP0R && dcrn < MAL0_RXCTP0R + mal->rxcnum) { + mal->rxctpr[dcrn - MAL0_RXCTP0R] = val; + } + if (dcrn >= MAL0_RCBS0 && dcrn < MAL0_RCBS0 + mal->rxcnum) { + mal->rcbs[dcrn - MAL0_RCBS0] = val & 0x000000FF; } } -static void ppc40x_mal_reset(void *opaque) -{ - ppc40x_mal_t *mal; - - mal = opaque; - mal->cfg = 0x0007C000; - mal->esr = 0x00000000; - mal->ier = 0x00000000; - mal->rxcasr = 0x00000000; - mal->rxdeir = 0x00000000; - mal->rxeobisr = 0x00000000; - mal->txcasr = 0x00000000; - mal->txdeir = 0x00000000; - mal->txeobisr = 0x00000000; -} - -void ppc405_mal_init(CPUPPCState *env, qemu_irq irqs[4]) +void ppc4xx_mal_init(CPUPPCState *env, uint8_t txcnum, uint8_t rxcnum, + qemu_irq irqs[4]) { - ppc40x_mal_t *mal; + ppc4xx_mal_t *mal; int i; - mal = g_malloc0(sizeof(ppc40x_mal_t)); + assert(txcnum <= 32 && rxcnum <= 32); + mal = g_malloc0(sizeof(*mal)); + mal->txcnum = txcnum; + mal->rxcnum = rxcnum; + mal->txctpr = g_new0(uint32_t, txcnum); + mal->rxctpr = g_new0(uint32_t, rxcnum); + mal->rcbs = g_new0(uint32_t, rxcnum); for (i = 0; i < 4; i++) { mal->irqs[i] = irqs[i]; } - qemu_register_reset(&ppc40x_mal_reset, mal); + qemu_register_reset(&ppc4xx_mal_reset, mal); ppc_dcr_register(env, MAL0_CFG, mal, &dcr_read_mal, &dcr_write_mal); ppc_dcr_register(env, MAL0_ESR, @@ -981,20 +948,16 @@ void ppc405_mal_init(CPUPPCState *env, qemu_irq irqs[4]) mal, &dcr_read_mal, &dcr_write_mal); ppc_dcr_register(env, MAL0_RXDEIR, mal, &dcr_read_mal, &dcr_write_mal); - ppc_dcr_register(env, MAL0_TXCTP0R, - mal, &dcr_read_mal, &dcr_write_mal); - ppc_dcr_register(env, MAL0_TXCTP1R, - mal, &dcr_read_mal, &dcr_write_mal); - ppc_dcr_register(env, MAL0_TXCTP2R, - mal, &dcr_read_mal, &dcr_write_mal); - ppc_dcr_register(env, MAL0_TXCTP3R, - mal, &dcr_read_mal, &dcr_write_mal); - ppc_dcr_register(env, MAL0_RXCTP0R, - mal, &dcr_read_mal, &dcr_write_mal); - ppc_dcr_register(env, MAL0_RXCTP1R, - mal, &dcr_read_mal, &dcr_write_mal); - ppc_dcr_register(env, MAL0_RCBS0, - mal, &dcr_read_mal, &dcr_write_mal); - ppc_dcr_register(env, MAL0_RCBS1, - mal, &dcr_read_mal, &dcr_write_mal); + for (i = 0; i < txcnum; i++) { + ppc_dcr_register(env, MAL0_TXCTP0R + i, + mal, &dcr_read_mal, &dcr_write_mal); + } + for (i = 0; i < rxcnum; i++) { + ppc_dcr_register(env, MAL0_RXCTP0R + i, + mal, &dcr_read_mal, &dcr_write_mal); + } + for (i = 0; i < rxcnum; i++) { + ppc_dcr_register(env, MAL0_RCBS0 + i, + mal, &dcr_read_mal, &dcr_write_mal); + } } diff --git a/include/hw/ppc/ppc4xx.h b/include/hw/ppc/ppc4xx.h index db50cfa..cb0bb55 100644 --- a/include/hw/ppc/ppc4xx.h +++ b/include/hw/ppc/ppc4xx.h @@ -53,7 +53,8 @@ void ppc4xx_sdram_init (CPUPPCState *env, qemu_irq irq, int nbanks, hwaddr *ram_sizes, int do_init); -void ppc405_mal_init(CPUPPCState *env, qemu_irq irqs[4]); +void ppc4xx_mal_init(CPUPPCState *env, uint8_t txcnum, uint8_t rxcnum, + qemu_irq irqs[4]); #define TYPE_PPC4xx_PCI_HOST_BRIDGE "ppc4xx-pcihost"