From patchwork Mon Dec 16 15:15:11 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Veith, Simon" X-Patchwork-Id: 1210494 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=quarantine dis=none) header.from=amazon.de Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=amazon.de header.i=@amazon.de header.b="ZjxCzYM8"; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 47c4lx5dQMz9sPT for ; Tue, 17 Dec 2019 02:23:09 +1100 (AEDT) Received: from localhost ([::1]:55500 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1igsDD-0001xf-LR for incoming@patchwork.ozlabs.org; Mon, 16 Dec 2019 10:23:07 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:54395) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1igs7b-0003oj-8Y for qemu-devel@nongnu.org; Mon, 16 Dec 2019 10:17:20 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1igs7a-0001qo-7b for qemu-devel@nongnu.org; Mon, 16 Dec 2019 10:17:19 -0500 Received: from smtp-fw-6001.amazon.com ([52.95.48.154]:28350) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1igs7Y-0001l9-1o; Mon, 16 Dec 2019 10:17:16 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amazon.de; i=@amazon.de; q=dns/txt; s=amazon201209; t=1576509437; x=1608045437; h=from:to:cc:subject:date:message-id:in-reply-to: references; bh=DnWdil9M/KHhlCYcqIHDhxnPOJB7mXEYpBcWYuPCZHo=; b=ZjxCzYM84JfFSa9Z9sQVZU8v82yo+3mc/KYDf/dWicJneZqF6m7OCMLM i+a0bM0xCBKERFwoekgt3ujBOPS1Ihp8jf+5C3bQwX04CBUDm32Zh7lzW L/1x23CX6GEuGdvREjVSNeaGVl4t2XHXhkqIK7RVHvcMRqPpqqxQ+g/9f 4=; IronPort-SDR: 7M0g3OtvPRRWfh9g4zkiGG3kZd7aWHFvz0OntyTUBMYpn+YRpnOA6OYJejATP9M7iTDGDeUOGx tzlI5LgVq5TQ== X-IronPort-AV: E=Sophos;i="5.69,322,1571702400"; d="scan'208";a="9275759" Received: from iad6-co-svc-p1-lb1-vlan3.amazon.com (HELO email-inbound-relay-2a-538b0bfb.us-west-2.amazon.com) ([10.124.125.6]) by smtp-border-fw-out-6001.iad6.amazon.com with ESMTP; 16 Dec 2019 15:17:15 +0000 Received: from sveith-desktop.aka.corp.amazon.com (pdx2-ws-svc-lb17-vlan2.amazon.com [10.247.140.66]) by email-inbound-relay-2a-538b0bfb.us-west-2.amazon.com (Postfix) with ESMTPS id 42F47A2651; Mon, 16 Dec 2019 15:17:13 +0000 (UTC) Received: from sveith-desktop.aka.corp.amazon.com (localhost [127.0.0.1]) by sveith-desktop.aka.corp.amazon.com (8.15.2/8.15.2/Debian-3) with ESMTP id xBGFHBbE014128; Mon, 16 Dec 2019 16:17:11 +0100 Received: (from sveith@localhost) by sveith-desktop.aka.corp.amazon.com (8.15.2/8.15.2/Submit) id xBGFHAp4014106; Mon, 16 Dec 2019 16:17:10 +0100 From: Simon Veith To: qemu-devel@nongnu.org, qemu-arm@nongnu.org Cc: Simon Veith , Eric Auger Subject: [PATCH v3 5/6] hw/arm/smmuv3: Use correct bit positions in EVT_SET_ADDR2 macro Date: Mon, 16 Dec 2019 16:15:11 +0100 Message-Id: <1576509312-13083-6-git-send-email-sveith@amazon.de> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1576509312-13083-1-git-send-email-sveith@amazon.de> References: <1576509312-13083-1-git-send-email-sveith@amazon.de> Precedence: Bulk X-detected-operating-system: by eggs.gnu.org: FreeBSD 9.x [fuzzy] X-Received-From: 52.95.48.154 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" The bit offsets in the EVT_SET_ADDR2 macro do not match those specified in the ARM SMMUv3 Architecture Specification. In all events that use this macro, e.g. F_WALK_EABT, the faulting fetch address or IPA actually occupies the 32-bit words 6 and 7 in the event record contiguously, with the upper and lower unused bits clear due to alignment or maximum supported address bits. How many bits are clear depends on the individual event type. Update the macro to write to the correct words in the event record so that guest drivers can obtain accurate address information on events. ref. ARM IHI 0070C, sections 7.3.12 through 7.3.16. Signed-off-by: Simon Veith Cc: Eric Auger Cc: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Acked-by: Eric Auger --- hw/arm/smmuv3-internal.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/hw/arm/smmuv3-internal.h b/hw/arm/smmuv3-internal.h index 042b435..4112394 100644 --- a/hw/arm/smmuv3-internal.h +++ b/hw/arm/smmuv3-internal.h @@ -461,8 +461,8 @@ typedef struct SMMUEventInfo { } while (0) #define EVT_SET_ADDR2(x, addr) \ do { \ - (x)->word[7] = deposit32((x)->word[7], 3, 29, addr >> 16); \ - (x)->word[7] = deposit32((x)->word[7], 0, 16, addr & 0xffff);\ + (x)->word[7] = (uint32_t)(addr >> 32); \ + (x)->word[6] = (uint32_t)(addr & 0xffffffff); \ } while (0) void smmuv3_record_event(SMMUv3State *s, SMMUEventInfo *event);