Message ID | 1566401321-22419-1-git-send-email-pc@us.ibm.com |
---|---|
State | New |
Headers | show |
Series | ppc: Fix xsmaddmdp and friends | expand |
On Wed, Aug 21, 2019 at 10:28:41AM -0500, Paul A. Clarke wrote: > From: "Paul A. Clarke" <pc@us.ibm.com> > > A class of instructions of the form: > op Target,A,B > which operate like: > Target = Target * A + B > have a bit set which distinguishes them from instructions that operate as: > Target = Target * B + A > > This bit is not being checked properly (using PPC_BIT macro), so all > instructions in this class are operating incorrectly as the second form > above. The bit was being checked as if it were part of a 64-bit > instruction opcode, rather than a proper 32-bit opcode. Fix by using the > macro (PPC_BIT32) which treats the opcode as a 32-bit quantity. > > Signed-off-by: Paul A. Clarke <pc@us.ibm.com> Applied to ppc-for-4.2, thanks. > --- > target/ppc/translate/vsx-impl.inc.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/target/ppc/translate/vsx-impl.inc.c b/target/ppc/translate/vsx-impl.inc.c > index 3922686..8287e27 100644 > --- a/target/ppc/translate/vsx-impl.inc.c > +++ b/target/ppc/translate/vsx-impl.inc.c > @@ -1308,7 +1308,7 @@ static void gen_##name(DisasContext *ctx) \ > } \ > xt = gen_vsr_ptr(xT(ctx->opcode)); \ > xa = gen_vsr_ptr(xA(ctx->opcode)); \ > - if (ctx->opcode & PPC_BIT(25)) { \ > + if (ctx->opcode & PPC_BIT32(25)) { \ > /* \ > * AxT + B \ > */ \
On 22/08/2019 00:56, David Gibson wrote: > On Wed, Aug 21, 2019 at 10:28:41AM -0500, Paul A. Clarke wrote: >> From: "Paul A. Clarke" <pc@us.ibm.com> >> >> A class of instructions of the form: >> op Target,A,B >> which operate like: >> Target = Target * A + B >> have a bit set which distinguishes them from instructions that operate as: >> Target = Target * B + A >> >> This bit is not being checked properly (using PPC_BIT macro), so all >> instructions in this class are operating incorrectly as the second form >> above. The bit was being checked as if it were part of a 64-bit >> instruction opcode, rather than a proper 32-bit opcode. Fix by using the >> macro (PPC_BIT32) which treats the opcode as a 32-bit quantity. >> >> Signed-off-by: Paul A. Clarke <pc@us.ibm.com> > > Applied to ppc-for-4.2, thanks. David, could you add: Fixes: c9f4e4d8b632 ("target/ppc: improve VSX_FMADD with new GEN_VSX_HELPER_VSX_MADD macro") Reviewed-by: Laurent Vivier <lvivier@redhat.com> Tested-by: Laurent Vivier <lvivier@redhat.com> Thanks, Laurent
On Wed, Aug 28, 2019 at 07:32:38PM +0200, Laurent Vivier wrote: > On 22/08/2019 00:56, David Gibson wrote: > > On Wed, Aug 21, 2019 at 10:28:41AM -0500, Paul A. Clarke wrote: > >> From: "Paul A. Clarke" <pc@us.ibm.com> > >> > >> A class of instructions of the form: > >> op Target,A,B > >> which operate like: > >> Target = Target * A + B > >> have a bit set which distinguishes them from instructions that operate as: > >> Target = Target * B + A > >> > >> This bit is not being checked properly (using PPC_BIT macro), so all > >> instructions in this class are operating incorrectly as the second form > >> above. The bit was being checked as if it were part of a 64-bit > >> instruction opcode, rather than a proper 32-bit opcode. Fix by using the > >> macro (PPC_BIT32) which treats the opcode as a 32-bit quantity. > >> > >> Signed-off-by: Paul A. Clarke <pc@us.ibm.com> > > > > Applied to ppc-for-4.2, thanks. > > David, > > could you add: > > Fixes: c9f4e4d8b632 ("target/ppc: improve VSX_FMADD with new GEN_VSX_HELPER_VSX_MADD macro") > > Reviewed-by: Laurent Vivier <lvivier@redhat.com> > Tested-by: Laurent Vivier <lvivier@redhat.com> Done, thanks.
diff --git a/target/ppc/translate/vsx-impl.inc.c b/target/ppc/translate/vsx-impl.inc.c index 3922686..8287e27 100644 --- a/target/ppc/translate/vsx-impl.inc.c +++ b/target/ppc/translate/vsx-impl.inc.c @@ -1308,7 +1308,7 @@ static void gen_##name(DisasContext *ctx) \ } \ xt = gen_vsr_ptr(xT(ctx->opcode)); \ xa = gen_vsr_ptr(xA(ctx->opcode)); \ - if (ctx->opcode & PPC_BIT(25)) { \ + if (ctx->opcode & PPC_BIT32(25)) { \ /* \ * AxT + B \ */ \