| Message ID | 1565163924-18621-10-git-send-email-bmeng.cn@gmail.com |
|---|---|
| State | Superseded |
| Headers | show |
| Series | [v2,01/28] riscv: hw: Remove superfluous "linux, phandle" property | expand |
On Wed, Aug 7, 2019 at 3:48 PM Bin Meng <bmeng.cn@gmail.com> wrote: > This updates the UART base address to match the hardware. > > Signed-off-by: Bin Meng <bmeng.cn@gmail.com> > Reviewed-by: Jonathan Behrens <fintelia@gmail.com> > Acked-by: Alistair Francis <alistair.francis@wdc.com> > --- > > Changes in v2: None > > hw/riscv/sifive_u.c | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c > index fe8dd3e..ea45e77 100644 > --- a/hw/riscv/sifive_u.c > +++ b/hw/riscv/sifive_u.c > @@ -61,8 +61,8 @@ static const struct MemmapEntry { > [SIFIVE_U_MROM] = { 0x1000, 0x11000 }, > [SIFIVE_U_CLINT] = { 0x2000000, 0x10000 }, > [SIFIVE_U_PLIC] = { 0xc000000, 0x4000000 }, > - [SIFIVE_U_UART0] = { 0x10013000, 0x1000 }, > - [SIFIVE_U_UART1] = { 0x10023000, 0x1000 }, > + [SIFIVE_U_UART0] = { 0x10010000, 0x1000 }, > + [SIFIVE_U_UART1] = { 0x10011000, 0x1000 }, > [SIFIVE_U_DRAM] = { 0x80000000, 0x0 }, > [SIFIVE_U_GEM] = { 0x100900FC, 0x2000 }, > }; > -- > 2.7.4 > > > By the way, OpenSBI also needs a patch to fix the same problem. Reviewed-by: Chih-Min Chao <chihmin.chao@sifive.com>
On Wed, Aug 7, 2019 at 5:25 PM Chih-Min Chao <chihmin.chao@sifive.com> wrote: > > > > On Wed, Aug 7, 2019 at 3:48 PM Bin Meng <bmeng.cn@gmail.com> wrote: >> >> This updates the UART base address to match the hardware. >> >> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> >> Reviewed-by: Jonathan Behrens <fintelia@gmail.com> >> Acked-by: Alistair Francis <alistair.francis@wdc.com> >> --- >> >> Changes in v2: None >> >> hw/riscv/sifive_u.c | 4 ++-- >> 1 file changed, 2 insertions(+), 2 deletions(-) >> >> diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c >> index fe8dd3e..ea45e77 100644 >> --- a/hw/riscv/sifive_u.c >> +++ b/hw/riscv/sifive_u.c >> @@ -61,8 +61,8 @@ static const struct MemmapEntry { >> [SIFIVE_U_MROM] = { 0x1000, 0x11000 }, >> [SIFIVE_U_CLINT] = { 0x2000000, 0x10000 }, >> [SIFIVE_U_PLIC] = { 0xc000000, 0x4000000 }, >> - [SIFIVE_U_UART0] = { 0x10013000, 0x1000 }, >> - [SIFIVE_U_UART1] = { 0x10023000, 0x1000 }, >> + [SIFIVE_U_UART0] = { 0x10010000, 0x1000 }, >> + [SIFIVE_U_UART1] = { 0x10011000, 0x1000 }, >> [SIFIVE_U_DRAM] = { 0x80000000, 0x0 }, >> [SIFIVE_U_GEM] = { 0x100900FC, 0x2000 }, >> }; >> -- >> 2.7.4 >> >> > > By the way, OpenSBI also needs a patch to fix the same problem. > No, with this series, sifive_u is not a special target any more and sifive/fu540 should be set to PLATFORM in the OpenSBI build for the 'sifive_u' machine. I will send a patch to OpenSBI to drop the 'sifive_u' support. > Reviewed-by: Chih-Min Chao <chihmin.chao@sifive.com> Regards, Bin
diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c index fe8dd3e..ea45e77 100644 --- a/hw/riscv/sifive_u.c +++ b/hw/riscv/sifive_u.c @@ -61,8 +61,8 @@ static const struct MemmapEntry { [SIFIVE_U_MROM] = { 0x1000, 0x11000 }, [SIFIVE_U_CLINT] = { 0x2000000, 0x10000 }, [SIFIVE_U_PLIC] = { 0xc000000, 0x4000000 }, - [SIFIVE_U_UART0] = { 0x10013000, 0x1000 }, - [SIFIVE_U_UART1] = { 0x10023000, 0x1000 }, + [SIFIVE_U_UART0] = { 0x10010000, 0x1000 }, + [SIFIVE_U_UART1] = { 0x10011000, 0x1000 }, [SIFIVE_U_DRAM] = { 0x80000000, 0x0 }, [SIFIVE_U_GEM] = { 0x100900FC, 0x2000 }, };