From patchwork Wed Jul 17 06:06:36 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tony Nguyen X-Patchwork-Id: 1133124 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=bt.com Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 45pRcC5S28z9sLt for ; Wed, 17 Jul 2019 16:06:51 +1000 (AEST) Received: from localhost ([::1]:54368 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hnd5V-0002VI-UP for incoming@patchwork.ozlabs.org; Wed, 17 Jul 2019 02:06:49 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:59588) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hnd5N-0002V0-OP for qemu-devel@nongnu.org; Wed, 17 Jul 2019 02:06:44 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hnd5L-000582-4x for qemu-devel@nongnu.org; Wed, 17 Jul 2019 02:06:41 -0400 Received: from smtpe1.intersmtp.com ([213.121.35.71]:3424) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1hnd5K-00057k-PN for qemu-devel@nongnu.org; Wed, 17 Jul 2019 02:06:39 -0400 Received: from tpw09926dag18f.domain1.systemhost.net (10.9.212.26) by BWP09926076.bt.com (10.36.82.107) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384_P256) id 15.1.1713.5; Wed, 17 Jul 2019 07:06:36 +0100 Received: from tpw09926dag18e.domain1.systemhost.net (10.9.212.18) by tpw09926dag18f.domain1.systemhost.net (10.9.212.26) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Wed, 17 Jul 2019 07:06:36 +0100 Received: from tpw09926dag18e.domain1.systemhost.net ([fe80::a946:6348:ccf4:fa6c]) by tpw09926dag18e.domain1.systemhost.net ([fe80::a946:6348:ccf4:fa6c%12]) with mapi id 15.00.1395.000; Wed, 17 Jul 2019 07:06:36 +0100 From: To: Thread-Topic: [Qemu-devel] [PATCH 2/4] memory: Single byte swap along the I/O path Thread-Index: AQHVPGXKIM8i1YWtwkykGX0aHoqHKA== Date: Wed, 17 Jul 2019 06:06:36 +0000 Message-ID: <1563343596429.3033@bt.com> References: In-Reply-To: Accept-Language: en-AU, en-GB, en-US Content-Language: en-AU X-MS-Has-Attach: X-MS-TNEF-Correlator: x-ms-exchange-transport-fromentityheader: Hosted x-originating-ip: [10.187.101.36] MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Windows 7 or 8 [fuzzy] X-Received-From: 213.121.35.71 Subject: [Qemu-devel] [PATCH 2/4] memory: Single byte swap along the I/O path X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: pbonzini@redhat.com, mark.cave-ayland@ilande.co.uk, atar4qemu@gmail.com, rth@twiddle.net Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Collapsed adjust_endianess and handle_bswap into the former. A single byte swap avoids redundant re-swapping. This is preparation for upcoming SPARC64 TTE invert endian bit which would be a third(!) byte swap along the I/O path. Signed-off-by: Tony Nguyen --- accel/tcg/cputlb.c | 58 +++++++++++++++++++--------------------- exec.c | 6 +++-- hw/intc/armv7m_nvic.c | 12 ++++----- hw/s390x/s390-pci-inst.c | 6 ++--- hw/vfio/pci-quirks.c | 4 +-- hw/virtio/virtio-pci.c | 6 +++-- include/exec/memop.h | 18 +++++++++++++ include/exec/memory.h | 9 ++++--- include/exec/poison.h | 1 - memory.c | 37 ++++++++++++++----------- memory_ldst.inc.c | 18 ++++++------- target/mips/op_helper.c | 4 +-- 12 files changed, 102 insertions(+), 77 deletions(-) diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index 523be4c848..baa61719ad 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -881,7 +881,7 @@ static void tlb_fill(CPUState *cpu, target_ulong addr, int size, static uint64_t io_readx(CPUArchState *env, CPUIOTLBEntry *iotlbentry, int mmu_idx, target_ulong addr, uintptr_t retaddr, - MMUAccessType access_type, int size) + MMUAccessType access_type, MemOp op) { CPUState *cpu = env_cpu(env); hwaddr mr_offset; @@ -906,14 +906,13 @@ static uint64_t io_readx(CPUArchState *env, CPUIOTLBEntry *iotlbentry, qemu_mutex_lock_iothread(); locked = true; } - r = memory_region_dispatch_read(mr, mr_offset, - &val, size, iotlbentry->attrs); + r = memory_region_dispatch_read(mr, mr_offset, &val, op, iotlbentry->attrs); if (r != MEMTX_OK) { hwaddr physaddr = mr_offset + section->offset_within_address_space - section->offset_within_region; - cpu_transaction_failed(cpu, physaddr, addr, size, access_type, + cpu_transaction_failed(cpu, physaddr, addr, MEMOP_SIZE(op), access_type, mmu_idx, iotlbentry->attrs, r, retaddr); } if (locked) { @@ -925,7 +924,7 @@ static uint64_t io_readx(CPUArchState *env, CPUIOTLBEntry *iotlbentry, static void io_writex(CPUArchState *env, CPUIOTLBEntry *iotlbentry, int mmu_idx, uint64_t val, target_ulong addr, - uintptr_t retaddr, int size) + uintptr_t retaddr, MemOp op) { CPUState *cpu = env_cpu(env); hwaddr mr_offset; @@ -947,15 +946,15 @@ static void io_writex(CPUArchState *env, CPUIOTLBEntry *iotlbentry, qemu_mutex_lock_iothread(); locked = true; } - r = memory_region_dispatch_write(mr, mr_offset, - val, size, iotlbentry->attrs); + r = memory_region_dispatch_write(mr, mr_offset, val, op, iotlbentry->attrs); if (r != MEMTX_OK) { hwaddr physaddr = mr_offset + section->offset_within_address_space - section->offset_within_region; - cpu_transaction_failed(cpu, physaddr, addr, size, MMU_DATA_STORE, - mmu_idx, iotlbentry->attrs, r, retaddr); + cpu_transaction_failed(cpu, physaddr, addr, MEMOP_SIZE(op), + MMU_DATA_STORE, mmu_idx, iotlbentry->attrs, r, + retaddr); } if (locked) { qemu_mutex_unlock_iothread(); @@ -1210,26 +1209,13 @@ static void *atomic_mmu_lookup(CPUArchState *env, target_ulong addr, #endif /* - * Byte Swap Helper + * Byte Swap Checker * - * This should all dead code away depending on the build host and - * access type. + * Dead code should all go away depending on the build host and access type. */ - -static inline uint64_t handle_bswap(uint64_t val, int size, bool big_endian) +static inline bool need_bswap(bool big_endian) { - if ((big_endian && NEED_BE_BSWAP) || (!big_endian && NEED_LE_BSWAP)) { - switch (size) { - case 1: return val; - case 2: return bswap16(val); - case 4: return bswap32(val); - case 8: return bswap64(val); - default: - g_assert_not_reached(); - } - } else { - return val; - } + return (big_endian && NEED_BE_BSWAP) || (!big_endian && NEED_LE_BSWAP); } /* @@ -1260,6 +1246,7 @@ load_helper(CPUArchState *env, target_ulong addr, TCGMemOpIdx oi, unsigned a_bits = get_alignment_bits(get_memop(oi)); void *haddr; uint64_t res; + MemOp op; /* Handle CPU specific unaligned behaviour */ if (addr & ((1 << a_bits) - 1)) { @@ -1305,9 +1292,13 @@ load_helper(CPUArchState *env, target_ulong addr, TCGMemOpIdx oi, } } - res = io_readx(env, &env_tlb(env)->d[mmu_idx].iotlb[index], - mmu_idx, addr, retaddr, access_type, size); - return handle_bswap(res, size, big_endian); + op = MEMOP(size); + if (need_bswap(big_endian)) { + op ^= MO_BSWAP; + } + + return io_readx(env, &env_tlb(env)->d[mmu_idx].iotlb[index], + mmu_idx, addr, retaddr, access_type, op); } /* Handle slow unaligned access (it spans two pages or IO). */ @@ -1508,6 +1499,7 @@ store_helper(CPUArchState *env, target_ulong addr, uint64_t val, const size_t tlb_off = offsetof(CPUTLBEntry, addr_write); unsigned a_bits = get_alignment_bits(get_memop(oi)); void *haddr; + MemOp op; /* Handle CPU specific unaligned behaviour */ if (addr & ((1 << a_bits) - 1)) { @@ -1553,9 +1545,13 @@ store_helper(CPUArchState *env, target_ulong addr, uint64_t val, } } + op = MEMOP(size); + if (need_bswap(big_endian)) { + op ^= MO_BSWAP; + } + io_writex(env, &env_tlb(env)->d[mmu_idx].iotlb[index], mmu_idx, - handle_bswap(val, size, big_endian), - addr, retaddr, size); + val, addr, retaddr, op); return; } diff --git a/exec.c b/exec.c index 3e78de3b8f..456e7ae02a 100644 --- a/exec.c +++ b/exec.c @@ -3334,7 +3334,8 @@ static MemTxResult flatview_write_continue(FlatView *fv, hwaddr addr, /* XXX: could force current_cpu to NULL to avoid potential bugs */ val = ldn_p(buf, l); - result |= memory_region_dispatch_write(mr, addr1, val, l, attrs); + result |= memory_region_dispatch_write(mr, addr1, val, MEMOP(l), + attrs); } else { /* RAM case */ ptr = qemu_ram_ptr_length(mr->ram_block, addr1, &l, false); @@ -3395,7 +3396,8 @@ MemTxResult flatview_read_continue(FlatView *fv, hwaddr addr, /* I/O case */ release_lock |= prepare_mmio_access(mr); l = memory_access_size(mr, l, addr1); - result |= memory_region_dispatch_read(mr, addr1, &val, l, attrs); + result |= memory_region_dispatch_read(mr, addr1, &val, MEMOP(l), + attrs); stn_p(buf, l, val); } else { /* RAM case */ diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c index 9f8f0d3ff5..7081e6e128 100644 --- a/hw/intc/armv7m_nvic.c +++ b/hw/intc/armv7m_nvic.c @@ -2337,7 +2337,7 @@ static const MemoryRegionOps nvic_sysreg_ops = { }; static MemTxResult nvic_sysreg_ns_write(void *opaque, hwaddr addr, - uint64_t value, unsigned size, + uint64_t data, unsigned size, MemTxAttrs attrs) { MemoryRegion *mr = opaque; @@ -2345,7 +2345,7 @@ static MemTxResult nvic_sysreg_ns_write(void *opaque, hwaddr addr, if (attrs.secure) { /* S accesses to the alias act like NS accesses to the real region */ attrs.secure = 0; - return memory_region_dispatch_write(mr, addr, value, size, attrs); + return memory_region_dispatch_write(mr, addr, data, MEMOP(size), attrs); } else { /* NS attrs are RAZ/WI for privileged, and BusFault for user */ if (attrs.user) { @@ -2364,7 +2364,7 @@ static MemTxResult nvic_sysreg_ns_read(void *opaque, hwaddr addr, if (attrs.secure) { /* S accesses to the alias act like NS accesses to the real region */ attrs.secure = 0; - return memory_region_dispatch_read(mr, addr, data, size, attrs); + return memory_region_dispatch_read(mr, addr, data, MEMOP(size), attrs); } else { /* NS attrs are RAZ/WI for privileged, and BusFault for user */ if (attrs.user) { @@ -2382,7 +2382,7 @@ static const MemoryRegionOps nvic_sysreg_ns_ops = { }; static MemTxResult nvic_systick_write(void *opaque, hwaddr addr, - uint64_t value, unsigned size, + uint64_t data, unsigned size, MemTxAttrs attrs) { NVICState *s = opaque; @@ -2390,7 +2390,7 @@ static MemTxResult nvic_systick_write(void *opaque, hwaddr addr, /* Direct the access to the correct systick */ mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->systick[attrs.secure]), 0); - return memory_region_dispatch_write(mr, addr, value, size, attrs); + return memory_region_dispatch_write(mr, addr, data, MEMOP(size), attrs); } static MemTxResult nvic_systick_read(void *opaque, hwaddr addr, @@ -2402,7 +2402,7 @@ static MemTxResult nvic_systick_read(void *opaque, hwaddr addr, /* Direct the access to the correct systick */ mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->systick[attrs.secure]), 0); - return memory_region_dispatch_read(mr, addr, data, size, attrs); + return memory_region_dispatch_read(mr, addr, data, MEMOP(size), attrs); } static const MemoryRegionOps nvic_systick_ops = { diff --git a/hw/s390x/s390-pci-inst.c b/hw/s390x/s390-pci-inst.c index 61f30b8e55..bf04fd2ed9 100644 --- a/hw/s390x/s390-pci-inst.c +++ b/hw/s390x/s390-pci-inst.c @@ -372,7 +372,7 @@ static MemTxResult zpci_read_bar(S390PCIBusDevice *pbdev, uint8_t pcias, mr = pbdev->pdev->io_regions[pcias].memory; mr = s390_get_subregion(mr, offset, len); offset -= mr->addr; - return memory_region_dispatch_read(mr, offset, data, len, + return memory_region_dispatch_read(mr, offset, data, MEMOP(len), MEMTXATTRS_UNSPECIFIED); } @@ -471,7 +471,7 @@ static MemTxResult zpci_write_bar(S390PCIBusDevice *pbdev, uint8_t pcias, mr = pbdev->pdev->io_regions[pcias].memory; mr = s390_get_subregion(mr, offset, len); offset -= mr->addr; - return memory_region_dispatch_write(mr, offset, data, len, + return memory_region_dispatch_write(mr, offset, data, MEMOP(len), MEMTXATTRS_UNSPECIFIED); } @@ -780,7 +780,7 @@ int pcistb_service_call(S390CPU *cpu, uint8_t r1, uint8_t r3, uint64_t gaddr, for (i = 0; i < len / 8; i++) { result = memory_region_dispatch_write(mr, offset + i * 8, - ldq_p(buffer + i * 8), 8, + ldq_p(buffer + i * 8), MO_64, MEMTXATTRS_UNSPECIFIED); if (result != MEMTX_OK) { s390_program_interrupt(env, PGM_OPERAND, 6, ra); diff --git a/hw/vfio/pci-quirks.c b/hw/vfio/pci-quirks.c index b35a640030..c8ed308700 100644 --- a/hw/vfio/pci-quirks.c +++ b/hw/vfio/pci-quirks.c @@ -1071,7 +1071,7 @@ static void vfio_rtl8168_quirk_address_write(void *opaque, hwaddr addr, /* Write to the proper guest MSI-X table instead */ memory_region_dispatch_write(&vdev->pdev.msix_table_mmio, - offset, val, size, + offset, val, MEMOP(size), MEMTXATTRS_UNSPECIFIED); } return; /* Do not write guest MSI-X data to hardware */ @@ -1102,7 +1102,7 @@ static uint64_t vfio_rtl8168_quirk_data_read(void *opaque, if (rtl->enabled && (vdev->pdev.cap_present & QEMU_PCI_CAP_MSIX)) { hwaddr offset = rtl->addr & 0xfff; memory_region_dispatch_read(&vdev->pdev.msix_table_mmio, offset, - &data, size, MEMTXATTRS_UNSPECIFIED); + &data, MEMOP(size), MEMTXATTRS_UNSPECIFIED); trace_vfio_quirk_rtl8168_msix_read(vdev->vbasedev.name, offset, data); } diff --git a/hw/virtio/virtio-pci.c b/hw/virtio/virtio-pci.c index ce928f2429..378ad6e94f 100644 --- a/hw/virtio/virtio-pci.c +++ b/hw/virtio/virtio-pci.c @@ -522,6 +522,7 @@ void virtio_address_space_write(VirtIOPCIProxy *proxy, hwaddr addr, { uint64_t val; MemoryRegion *mr; + MemOp op = MEMOP(len); /* address_space_* APIs assume an aligned address. * As address is under guest control, handle illegal values. @@ -550,7 +551,7 @@ void virtio_address_space_write(VirtIOPCIProxy *proxy, hwaddr addr, /* As length is under guest control, handle illegal values. */ return; } - memory_region_dispatch_write(mr, addr, val, len, MEMTXATTRS_UNSPECIFIED); + memory_region_dispatch_write(mr, addr, val, op, MEMTXATTRS_UNSPECIFIED); } static void @@ -559,6 +560,7 @@ virtio_address_space_read(VirtIOPCIProxy *proxy, hwaddr addr, { uint64_t val; MemoryRegion *mr; + MemOp op = MEMOP(len); /* address_space_* APIs assume an aligned address. * As address is under guest control, handle illegal values. @@ -573,7 +575,7 @@ virtio_address_space_read(VirtIOPCIProxy *proxy, hwaddr addr, /* Make sure caller aligned buf properly */ assert(!(((uintptr_t)buf) & (len - 1))); - memory_region_dispatch_read(mr, addr, &val, len, MEMTXATTRS_UNSPECIFIED); + memory_region_dispatch_read(mr, addr, &val, op, MEMTXATTRS_UNSPECIFIED); switch (len) { case 1: pci_set_byte(buf, val); diff --git a/include/exec/memop.h b/include/exec/memop.h index 54a75053ae..4a2eb02b13 100644 --- a/include/exec/memop.h +++ b/include/exec/memop.h @@ -100,4 +100,22 @@ typedef enum MemOp { MO_SSIZE = MO_SIZE | MO_SIGN, } MemOp; +#define MEMOP_SIZE(op) (1 << ((op) & MO_SIZE)) + +static inline MemOp MEMOP(unsigned size) +{ + switch (size) { + case 1: + return MO_8; + case 2: + return MO_16; + case 4: + return MO_32; + case 8: + return MO_64; + default: + g_assert_not_reached(); + } +} + #endif diff --git a/include/exec/memory.h b/include/exec/memory.h index bb0961ddb9..30b1c58123 100644 --- a/include/exec/memory.h +++ b/include/exec/memory.h @@ -19,6 +19,7 @@ #include "exec/cpu-common.h" #include "exec/hwaddr.h" #include "exec/memattrs.h" +#include "exec/memop.h" #include "exec/ramlist.h" #include "qemu/queue.h" #include "qemu/int128.h" @@ -1731,13 +1732,13 @@ void mtree_info(bool flatview, bool dispatch_tree, bool owner); * @mr: #MemoryRegion to access * @addr: address within that region * @pval: pointer to uint64_t which the data is written to - * @size: size of the access in bytes + * @op: encodes size of the access in bytes * @attrs: memory transaction attributes to use for the access */ MemTxResult memory_region_dispatch_read(MemoryRegion *mr, hwaddr addr, uint64_t *pval, - unsigned size, + MemOp op, MemTxAttrs attrs); /** * memory_region_dispatch_write: perform a write directly to the specified @@ -1746,13 +1747,13 @@ MemTxResult memory_region_dispatch_read(MemoryRegion *mr, * @mr: #MemoryRegion to access * @addr: address within that region * @data: data to write - * @size: size of the access in bytes + * @op: encodes size of the access in bytes * @attrs: memory transaction attributes to use for the access */ MemTxResult memory_region_dispatch_write(MemoryRegion *mr, hwaddr addr, uint64_t data, - unsigned size, + MemOp op, MemTxAttrs attrs); /** diff --git a/include/exec/poison.h b/include/exec/poison.h index b862320fa6..ab5a864869 100644 --- a/include/exec/poison.h +++ b/include/exec/poison.h @@ -38,7 +38,6 @@ #pragma GCC poison TARGET_HAS_BFLT #pragma GCC poison TARGET_NAME #pragma GCC poison TARGET_SUPPORTS_MTTCG -#pragma GCC poison TARGET_WORDS_BIGENDIAN #pragma GCC poison BSWAP_NEEDED #pragma GCC poison TARGET_LONG_BITS diff --git a/memory.c b/memory.c index d4579bbaec..72c494fbe1 100644 --- a/memory.c +++ b/memory.c @@ -350,7 +350,7 @@ static bool memory_region_big_endian(MemoryRegion *mr) #endif } -static bool memory_region_wrong_endianness(MemoryRegion *mr) +static bool memory_region_endianness_inverted(MemoryRegion *mr) { #ifdef TARGET_WORDS_BIGENDIAN return mr->ops->endianness == DEVICE_LITTLE_ENDIAN; @@ -359,23 +359,27 @@ static bool memory_region_wrong_endianness(MemoryRegion *mr) #endif } -static void adjust_endianness(MemoryRegion *mr, uint64_t *data, unsigned size) +static void adjust_endianness(MemoryRegion *mr, uint64_t *data, MemOp op) { - if (memory_region_wrong_endianness(mr)) { - switch (size) { - case 1: + if (memory_region_endianness_inverted(mr)) { + op ^= MO_BSWAP; + } + + if (op & MO_BSWAP) { + switch (op & MO_SIZE) { + case MO_8: break; - case 2: + case MO_16: *data = bswap16(*data); break; - case 4: + case MO_32: *data = bswap32(*data); break; - case 8: + case MO_64: *data = bswap64(*data); break; default: - abort(); + g_assert_not_reached(); } } } @@ -1437,10 +1441,11 @@ static MemTxResult memory_region_dispatch_read1(MemoryRegion *mr, MemTxResult memory_region_dispatch_read(MemoryRegion *mr, hwaddr addr, uint64_t *pval, - unsigned size, + MemOp op, MemTxAttrs attrs) { MemTxResult r; + unsigned size = MEMOP_SIZE(op); if (!memory_region_access_valid(mr, addr, size, false, attrs)) { *pval = unassigned_mem_read(mr, addr, size); @@ -1448,7 +1453,7 @@ MemTxResult memory_region_dispatch_read(MemoryRegion *mr, } r = memory_region_dispatch_read1(mr, addr, pval, size, attrs); - adjust_endianness(mr, pval, size); + adjust_endianness(mr, pval, op); return r; } @@ -1481,15 +1486,17 @@ static bool memory_region_dispatch_write_eventfds(MemoryRegion *mr, MemTxResult memory_region_dispatch_write(MemoryRegion *mr, hwaddr addr, uint64_t data, - unsigned size, + MemOp op, MemTxAttrs attrs) { + unsigned size = MEMOP_SIZE(op); + if (!memory_region_access_valid(mr, addr, size, true, attrs)) { unassigned_mem_write(mr, addr, data, size); return MEMTX_DECODE_ERROR; } - adjust_endianness(mr, &data, size); + adjust_endianness(mr, &data, op); if ((!kvm_eventfds_enabled()) && memory_region_dispatch_write_eventfds(mr, addr, data, size, attrs)) { @@ -2335,7 +2342,7 @@ void memory_region_add_eventfd(MemoryRegion *mr, } if (size) { - adjust_endianness(mr, &mrfd.data, size); + adjust_endianness(mr, &mrfd.data, MEMOP(size)); } memory_region_transaction_begin(); for (i = 0; i < mr->ioeventfd_nb; ++i) { @@ -2370,7 +2377,7 @@ void memory_region_del_eventfd(MemoryRegion *mr, unsigned i; if (size) { - adjust_endianness(mr, &mrfd.data, size); + adjust_endianness(mr, &mrfd.data, MEMOP(size)); } memory_region_transaction_begin(); for (i = 0; i < mr->ioeventfd_nb; ++i) { diff --git a/memory_ldst.inc.c b/memory_ldst.inc.c index acf865b900..de658c40c4 100644 --- a/memory_ldst.inc.c +++ b/memory_ldst.inc.c @@ -38,7 +38,7 @@ static inline uint32_t glue(address_space_ldl_internal, SUFFIX)(ARG1_DECL, release_lock |= prepare_mmio_access(mr); /* I/O case */ - r = memory_region_dispatch_read(mr, addr1, &val, 4, attrs); + r = memory_region_dispatch_read(mr, addr1, &val, MO_32, attrs); #if defined(TARGET_WORDS_BIGENDIAN) if (endian == DEVICE_LITTLE_ENDIAN) { val = bswap32(val); @@ -114,7 +114,7 @@ static inline uint64_t glue(address_space_ldq_internal, SUFFIX)(ARG1_DECL, release_lock |= prepare_mmio_access(mr); /* I/O case */ - r = memory_region_dispatch_read(mr, addr1, &val, 8, attrs); + r = memory_region_dispatch_read(mr, addr1, &val, MO_64, attrs); #if defined(TARGET_WORDS_BIGENDIAN) if (endian == DEVICE_LITTLE_ENDIAN) { val = bswap64(val); @@ -188,7 +188,7 @@ uint32_t glue(address_space_ldub, SUFFIX)(ARG1_DECL, release_lock |= prepare_mmio_access(mr); /* I/O case */ - r = memory_region_dispatch_read(mr, addr1, &val, 1, attrs); + r = memory_region_dispatch_read(mr, addr1, &val, MO_8, attrs); } else { /* RAM case */ ptr = qemu_map_ram_ptr(mr->ram_block, addr1); @@ -224,7 +224,7 @@ static inline uint32_t glue(address_space_lduw_internal, SUFFIX)(ARG1_DECL, release_lock |= prepare_mmio_access(mr); /* I/O case */ - r = memory_region_dispatch_read(mr, addr1, &val, 2, attrs); + r = memory_region_dispatch_read(mr, addr1, &val, MO_16, attrs); #if defined(TARGET_WORDS_BIGENDIAN) if (endian == DEVICE_LITTLE_ENDIAN) { val = bswap16(val); @@ -300,7 +300,7 @@ void glue(address_space_stl_notdirty, SUFFIX)(ARG1_DECL, if (l < 4 || !memory_access_is_direct(mr, true)) { release_lock |= prepare_mmio_access(mr); - r = memory_region_dispatch_write(mr, addr1, val, 4, attrs); + r = memory_region_dispatch_write(mr, addr1, val, MO_32, attrs); } else { ptr = qemu_map_ram_ptr(mr->ram_block, addr1); stl_p(ptr, val); @@ -346,7 +346,7 @@ static inline void glue(address_space_stl_internal, SUFFIX)(ARG1_DECL, val = bswap32(val); } #endif - r = memory_region_dispatch_write(mr, addr1, val, 4, attrs); + r = memory_region_dispatch_write(mr, addr1, val, MO_32, attrs); } else { /* RAM case */ ptr = qemu_map_ram_ptr(mr->ram_block, addr1); @@ -408,7 +408,7 @@ void glue(address_space_stb, SUFFIX)(ARG1_DECL, mr = TRANSLATE(addr, &addr1, &l, true, attrs); if (!memory_access_is_direct(mr, true)) { release_lock |= prepare_mmio_access(mr); - r = memory_region_dispatch_write(mr, addr1, val, 1, attrs); + r = memory_region_dispatch_write(mr, addr1, val, MO_8, attrs); } else { /* RAM case */ ptr = qemu_map_ram_ptr(mr->ram_block, addr1); @@ -451,7 +451,7 @@ static inline void glue(address_space_stw_internal, SUFFIX)(ARG1_DECL, val = bswap16(val); } #endif - r = memory_region_dispatch_write(mr, addr1, val, 2, attrs); + r = memory_region_dispatch_write(mr, addr1, val, MO_16, attrs); } else { /* RAM case */ ptr = qemu_map_ram_ptr(mr->ram_block, addr1); @@ -524,7 +524,7 @@ static void glue(address_space_stq_internal, SUFFIX)(ARG1_DECL, val = bswap64(val); } #endif - r = memory_region_dispatch_write(mr, addr1, val, 8, attrs); + r = memory_region_dispatch_write(mr, addr1, val, MO_64, attrs); } else { /* RAM case */ ptr = qemu_map_ram_ptr(mr->ram_block, addr1); diff --git a/target/mips/op_helper.c b/target/mips/op_helper.c index 9e2e02f858..2fc9803f7b 100644 --- a/target/mips/op_helper.c +++ b/target/mips/op_helper.c @@ -4740,11 +4740,11 @@ void helper_cache(CPUMIPSState *env, target_ulong addr, uint32_t op) if (op == 9) { /* Index Store Tag */ memory_region_dispatch_write(env->itc_tag, index, env->CP0_TagLo, - 8, MEMTXATTRS_UNSPECIFIED); + MO_64, MEMTXATTRS_UNSPECIFIED); } else if (op == 5) { /* Index Load Tag */ memory_region_dispatch_read(env->itc_tag, index, &env->CP0_TagLo, - 8, MEMTXATTRS_UNSPECIFIED); + MO_64, MEMTXATTRS_UNSPECIFIED); } #endif }