From patchwork Fri Jul 5 11:01:37 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yi Liu X-Patchwork-Id: 1128436 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=intel.com Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 45gq6K0SVCz9sNf for ; Sat, 6 Jul 2019 21:21:25 +1000 (AEST) Received: from localhost ([::1]:58746 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hjikt-0002pu-FO for incoming@patchwork.ozlabs.org; Sat, 06 Jul 2019 07:21:23 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:52351) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hjiie-0002pC-Ej for qemu-devel@nongnu.org; Sat, 06 Jul 2019 07:19:05 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hjiid-0005rA-9H for qemu-devel@nongnu.org; Sat, 06 Jul 2019 07:19:04 -0400 Received: from mga14.intel.com ([192.55.52.115]:2961) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1hjiid-0005e0-0i for qemu-devel@nongnu.org; Sat, 06 Jul 2019 07:19:03 -0400 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by fmsmga103.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 06 Jul 2019 04:19:01 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.63,458,1557212400"; d="scan'208";a="363354982" Received: from yiliu-dev.bj.intel.com ([10.238.156.139]) by fmsmga005.fm.intel.com with ESMTP; 06 Jul 2019 04:18:59 -0700 From: Liu Yi L To: qemu-devel@nongnu.org, mst@redhat.com, pbonzini@redhat.com, alex.williamson@redhat.com, peterx@redhat.com Date: Fri, 5 Jul 2019 19:01:37 +0800 Message-Id: <1562324511-2910-5-git-send-email-yi.l.liu@intel.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1562324511-2910-1-git-send-email-yi.l.liu@intel.com> References: <1562324511-2910-1-git-send-email-yi.l.liu@intel.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 192.55.52.115 Subject: [Qemu-devel] [RFC v1 04/18] intel_iommu: add "sm_model" option X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: tianyu.lan@intel.com, kevin.tian@intel.com, yi.l.liu@intel.com, Yi Sun , kvm@vger.kernel.org, jun.j.tian@intel.com, eric.auger@redhat.com, yi.y.sun@intel.com, Jacob Pan , david@gibson.dropbear.id.au Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Intel VT-d 3.0 introduces scalable mode, and it has a bunch of capabilities related to scalable mode translation, thus there are multiple combinations. While this vIOMMU implementation wants simplify it for user by providing typical combinations. User could config it by "sm_model" option. The usage is as below: "-device intel-iommu,x-scalable-mode=on,sm_model=["legacy"|"scalable"]" - "legacy": gives support for SL page table - "scalable": gives support for FL page table, pasid, virtual command - default to be "legacy" if "x-scalable-mode=on while no sm_model is configured Cc: Kevin Tian Cc: Jacob Pan Cc: Peter Xu Cc: Yi Sun Signed-off-by: Liu Yi L Signed-off-by: Yi Sun --- hw/i386/intel_iommu.c | 28 +++++++++++++++++++++++++++- hw/i386/intel_iommu_internal.h | 2 ++ include/hw/i386/intel_iommu.h | 1 + 3 files changed, 30 insertions(+), 1 deletion(-) diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c index 44b1231..3160a05 100644 --- a/hw/i386/intel_iommu.c +++ b/hw/i386/intel_iommu.c @@ -3014,6 +3014,7 @@ static Property vtd_properties[] = { DEFINE_PROP_BOOL("caching-mode", IntelIOMMUState, caching_mode, FALSE), DEFINE_PROP_BOOL("x-scalable-mode", IntelIOMMUState, scalable_mode, FALSE), DEFINE_PROP_BOOL("dma-drain", IntelIOMMUState, dma_drain, true), + DEFINE_PROP_STRING("sm_model", IntelIOMMUState, sm_model), DEFINE_PROP_END_OF_LIST(), }; @@ -3489,6 +3490,14 @@ static void vtd_iommu_replay(IOMMUMemoryRegion *iommu_mr, IOMMUNotifier *n) return; } +const char sm_model_manual[] = + "\"-device intel-iommu,x-scalable-mode=on," + "sm_model=[\"legacy\"|\"scalable\"]\"\n" + " - \"legacy\" gives support for SL page table based IOVA\n" + " - \"scalable\" gives support for FL page table based IOVA and SVA\n" + " - default to be \"legacy\" if \"x-scalable-mode=on\"" + " while no sm_model is configured\n"; + /* Do the initialization. It will also be called when reset, so pay * attention when adding new initialization stuff. */ @@ -3557,9 +3566,26 @@ static void vtd_init(IntelIOMMUState *s) s->cap |= VTD_CAP_CM; } + if (s->sm_model && !s->scalable_mode) { + printf("\n\"sm_model\" depends on \"x-scalable-mode\"\n" + "please check if \"x-scalable-mode\" is expected\n" + "\"sm_model\" manual:\n%s", sm_model_manual); + exit(1); + } + /* TODO: read cap/ecap from host to decide which cap to be exposed. */ if (s->scalable_mode) { - s->ecap |= VTD_ECAP_SMTS | VTD_ECAP_SRS | VTD_ECAP_SLTS; + if (!s->sm_model || !strcmp(s->sm_model, "legacy")) { + s->ecap |= VTD_ECAP_SMTS | VTD_ECAP_SRS | VTD_ECAP_SLTS; + } else if (!strcmp(s->sm_model, "scalable")) { + s->ecap |= VTD_ECAP_SMTS | VTD_ECAP_SRS | VTD_ECAP_PASID + | VTD_ECAP_FLTS; + } else { + printf("\n!!!!! Invalid sm_model config !!!!!\n" + "Please config sm_model=[\"legacy\"|\"scalable\"]\n" + "\"sm_model\" manual:\n%s", sm_model_manual); + exit(1); + } } vtd_reset_caches(s); diff --git a/hw/i386/intel_iommu_internal.h b/hw/i386/intel_iommu_internal.h index c1235a7..adae198 100644 --- a/hw/i386/intel_iommu_internal.h +++ b/hw/i386/intel_iommu_internal.h @@ -190,8 +190,10 @@ #define VTD_ECAP_PT (1ULL << 6) #define VTD_ECAP_MHMV (15ULL << 20) #define VTD_ECAP_SRS (1ULL << 31) +#define VTD_ECAP_PASID (1ULL << 40) #define VTD_ECAP_SMTS (1ULL << 43) #define VTD_ECAP_SLTS (1ULL << 46) +#define VTD_ECAP_FLTS (1ULL << 47) /* CAP_REG */ /* (offset >> 4) << 24 */ diff --git a/include/hw/i386/intel_iommu.h b/include/hw/i386/intel_iommu.h index 12f3d26..b51cc9f 100644 --- a/include/hw/i386/intel_iommu.h +++ b/include/hw/i386/intel_iommu.h @@ -270,6 +270,7 @@ struct IntelIOMMUState { bool buggy_eim; /* Force buggy EIM unless eim=off */ uint8_t aw_bits; /* Host/IOVA address width (in bits) */ bool dma_drain; /* Whether DMA r/w draining enabled */ + char *sm_model; /* identify actual scalable mode iommu model*/ /* * Protects IOMMU states in general. Currently it protects the