@@ -29,7 +29,7 @@
#define TIMER_PERIOD 10 /* 10 ns period for 100 Mhz frequency */
/* XXX: do not use a global */
-uint32_t cpu_mips_get_random (CPUMIPSState *env)
+uint32_t cpu_mips_get_random(CPUMIPSState *env)
{
static uint32_t seed = 1;
static uint32_t prev_idx = 0;
@@ -73,7 +73,7 @@ static void cpu_mips_timer_expire(CPUMIPSState *env)
qemu_irq_raise(env->irq[(env->CP0_IntCtl >> CP0IntCtl_IPTI) & 0x7]);
}
-uint32_t cpu_mips_get_count (CPUMIPSState *env)
+uint32_t cpu_mips_get_count(CPUMIPSState *env)
{
if (env->CP0_Cause & (1 << CP0Ca_DC)) {
return env->CP0_Count;
@@ -91,7 +91,7 @@ uint32_t cpu_mips_get_count (CPUMIPSState *env)
}
}
-void cpu_mips_store_count (CPUMIPSState *env, uint32_t count)
+void cpu_mips_store_count(CPUMIPSState *env, uint32_t count)
{
/*
* This gets called from cpu_state_reset(), potentially before timer init.
@@ -109,7 +109,7 @@ void cpu_mips_store_count (CPUMIPSState *env, uint32_t count)
}
}
-void cpu_mips_store_compare (CPUMIPSState *env, uint32_t value)
+void cpu_mips_store_compare(CPUMIPSState *env, uint32_t value)
{
env->CP0_Compare = value;
if (!(env->CP0_Cause & (1 << CP0Ca_DC)))
@@ -131,7 +131,7 @@ void cpu_mips_stop_count(CPUMIPSState *env)
TIMER_PERIOD);
}
-static void mips_timer_cb (void *opaque)
+static void mips_timer_cb(void *opaque)
{
CPUMIPSState *env;
@@ -151,7 +151,7 @@ static void mips_timer_cb (void *opaque)
env->CP0_Count--;
}
-void cpu_mips_clock_init (MIPSCPU *cpu)
+void cpu_mips_clock_init(MIPSCPU *cpu)
{
CPUMIPSState *env = &cpu->env;