From patchwork Mon Mar 25 14:52:40 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mateja Marjanovic X-Patchwork-Id: 1064427 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=rt-rk.com Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 44SckD6zxvz9sSh for ; Tue, 26 Mar 2019 01:55:00 +1100 (AEDT) Received: from localhost ([127.0.0.1]:43735 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1h8R06-0004tN-SA for incoming@patchwork.ozlabs.org; Mon, 25 Mar 2019 10:54:58 -0400 Received: from eggs.gnu.org ([209.51.188.92]:47941) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1h8Qz9-0004qZ-DL for qemu-devel@nongnu.org; Mon, 25 Mar 2019 10:54:00 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1h8Qz8-0003vH-8E for qemu-devel@nongnu.org; Mon, 25 Mar 2019 10:53:59 -0400 Received: from mx2.rt-rk.com ([89.216.37.149]:47553 helo=mail.rt-rk.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1h8Qz7-0003bU-RG for qemu-devel@nongnu.org; Mon, 25 Mar 2019 10:53:58 -0400 Received: from localhost (localhost [127.0.0.1]) by mail.rt-rk.com (Postfix) with ESMTP id D97AC1A2078; Mon, 25 Mar 2019 15:52:54 +0100 (CET) X-Virus-Scanned: amavisd-new at rt-rk.com Received: from rtrkw310-lin.domain.local (rtrkw310-lin.domain.local [10.10.13.97]) by mail.rt-rk.com (Postfix) with ESMTPSA id B32F11A1F81; Mon, 25 Mar 2019 15:52:54 +0100 (CET) From: Mateja Marjanovic To: qemu-devel@nongnu.org Date: Mon, 25 Mar 2019 15:52:40 +0100 Message-Id: <1553525566-14913-2-git-send-email-mateja.marjanovic@rt-rk.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1553525566-14913-1-git-send-email-mateja.marjanovic@rt-rk.com> References: <1553525566-14913-1-git-send-email-mateja.marjanovic@rt-rk.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x X-Received-From: 89.216.37.149 Subject: [Qemu-devel] [PATCH v2 1/7] target/mips: Fix . MSA instructions for MIPS big endian host X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: arikalo@wavecomp.com, amarkovic@wavecomp.com, aurelien@aurel32.net Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" From: Mateja Marjanovic Load and store MSA instructions when executed on a MIPS big endian CPU, didn't change the endianness, and were behaving like on little endian. Signed-off-by: Mateja Marjanovic --- target/mips/op_helper.c | 79 ++++++++++++++++++++++++++++++++++--------------- 1 file changed, 55 insertions(+), 24 deletions(-) diff --git a/target/mips/op_helper.c b/target/mips/op_helper.c index 0f272a5..5441ab2 100644 --- a/target/mips/op_helper.c +++ b/target/mips/op_helper.c @@ -4371,18 +4371,37 @@ FOP_CONDN_S(sne, (float32_lt(fst1, fst0, &env->active_fpu.fp_status) #define MEMOP_IDX(DF) #endif -#define MSA_LD_DF(DF, TYPE, LD_INSN, ...) \ -void helper_msa_ld_ ## TYPE(CPUMIPSState *env, uint32_t wd, \ - target_ulong addr) \ -{ \ - wr_t *pwd = &(env->active_fpu.fpr[wd].wr); \ - wr_t wx; \ - int i; \ - MEMOP_IDX(DF) \ - for (i = 0; i < DF_ELEMENTS(DF); i++) { \ - wx.TYPE[i] = LD_INSN(env, addr + (i << DF), ##__VA_ARGS__); \ - } \ - memcpy(pwd, &wx, sizeof(wr_t)); \ +#if defined(HOST_WORDS_BIGENDIAN) + bool big_endian = 1; +#else + bool big_endian = 0; +#endif + +#define MSA_LD_DF(DF, TYPE, LD_INSN, ...) \ +void helper_msa_ld_ ## TYPE(CPUMIPSState *env, uint32_t wd, \ + target_ulong addr) \ +{ \ + wr_t *pwd = &(env->active_fpu.fpr[wd].wr); \ + wr_t wx; \ + int i, k; \ + MEMOP_IDX(DF) \ + if (!big_endian) { \ + for (i = 0; i < DF_ELEMENTS(DF); i++) { \ + wx.TYPE[i] = LD_INSN(env, addr + (i << DF), ##__VA_ARGS__); \ + } \ + } else { \ + for (i = 0; i < DF_ELEMENTS(DF); i++) { \ + if (i < DF_ELEMENTS(DF) / 2) { \ + k = DF_ELEMENTS(DF) / 2 - i - 1; \ + wx.TYPE[i] = LD_INSN(env, addr + (k << DF), ##__VA_ARGS__); \ + } else { \ + k = 3 * DF_ELEMENTS(DF) / 2 - i - 1; \ + wx.TYPE[i] = LD_INSN(env, addr + (k << DF), ##__VA_ARGS__); \ + } \ + } \ + } \ + \ + memcpy(pwd, &wx, sizeof(wr_t)); \ } #if !defined(CONFIG_USER_ONLY) @@ -4417,18 +4436,30 @@ static inline void ensure_writable_pages(CPUMIPSState *env, #endif } -#define MSA_ST_DF(DF, TYPE, ST_INSN, ...) \ -void helper_msa_st_ ## TYPE(CPUMIPSState *env, uint32_t wd, \ - target_ulong addr) \ -{ \ - wr_t *pwd = &(env->active_fpu.fpr[wd].wr); \ - int mmu_idx = cpu_mmu_index(env, false); \ - int i; \ - MEMOP_IDX(DF) \ - ensure_writable_pages(env, addr, mmu_idx, GETPC()); \ - for (i = 0; i < DF_ELEMENTS(DF); i++) { \ - ST_INSN(env, addr + (i << DF), pwd->TYPE[i], ##__VA_ARGS__); \ - } \ +#define MSA_ST_DF(DF, TYPE, ST_INSN, ...) \ +void helper_msa_st_ ## TYPE(CPUMIPSState *env, uint32_t wd, \ + target_ulong addr) \ +{ \ + wr_t *pwd = &(env->active_fpu.fpr[wd].wr); \ + int mmu_idx = cpu_mmu_index(env, false); \ + int i, k; \ + MEMOP_IDX(DF) \ + ensure_writable_pages(env, addr, mmu_idx, GETPC()); \ + if (!big_endian) { \ + for (i = 0; i < DF_ELEMENTS(DF); i++) { \ + ST_INSN(env, addr + (i << DF), pwd->TYPE[i], ##__VA_ARGS__); \ + } \ + } else { \ + for (i = 0; i < DF_ELEMENTS(DF); i++) { \ + if (i < DF_ELEMENTS(DF) / 2) { \ + k = DF_ELEMENTS(DF) / 2 - i - 1; \ + ST_INSN(env, addr + (k << DF), pwd->TYPE[i], ##__VA_ARGS__); \ + } else { \ + k = 3 * DF_ELEMENTS(DF) / 2 - i - 1; \ + ST_INSN(env, addr + (k << DF), pwd->TYPE[i], ##__VA_ARGS__); \ + } \ + } \ + } \ } #if !defined(CONFIG_USER_ONLY)