From patchwork Tue Mar 5 18:05:19 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Aleksandar Markovic X-Patchwork-Id: 1051914 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=rt-rk.com Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 44DPy10gnsz9sBp for ; Wed, 6 Mar 2019 05:07:53 +1100 (AEDT) Received: from localhost ([127.0.0.1]:47110 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1h1ETm-0001DO-WE for incoming@patchwork.ozlabs.org; Tue, 05 Mar 2019 13:07:51 -0500 Received: from eggs.gnu.org ([209.51.188.92]:47005) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1h1ESk-0001Aj-7z for qemu-devel@nongnu.org; Tue, 05 Mar 2019 13:06:47 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1h1ESj-0002AY-7l for qemu-devel@nongnu.org; Tue, 05 Mar 2019 13:06:46 -0500 Received: from mx2.rt-rk.com ([89.216.37.149]:51691 helo=mail.rt-rk.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1h1ESi-00028M-6N for qemu-devel@nongnu.org; Tue, 05 Mar 2019 13:06:44 -0500 Received: from localhost (localhost [127.0.0.1]) by mail.rt-rk.com (Postfix) with ESMTP id DE6021A20D2; Tue, 5 Mar 2019 19:05:37 +0100 (CET) X-Virus-Scanned: amavisd-new at rt-rk.com Received: from rtrkw774-lin.domain.local (rtrkw774-lin.domain.local [10.10.13.43]) by mail.rt-rk.com (Postfix) with ESMTPSA id 794AE1A20D7; Tue, 5 Mar 2019 19:05:37 +0100 (CET) From: Aleksandar Markovic To: qemu-devel@nongnu.org Date: Tue, 5 Mar 2019 19:05:19 +0100 Message-Id: <1551809127-3658-8-git-send-email-aleksandar.markovic@rt-rk.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1551809127-3658-1-git-send-email-aleksandar.markovic@rt-rk.com> References: <1551809127-3658-1-git-send-email-aleksandar.markovic@rt-rk.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x X-Received-From: 89.216.37.149 Subject: [Qemu-devel] [PULL 07/15] tests/tcg: target/mips: Extend functionality of MSA wrapper macros X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, amarkovic@wavecomp.com Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" From: Aleksandar Markovic Add macros that will allow testing cases when one of the source registers is identical to the destination register. Signed-off-by: Aleksandar Markovic Reviewed-by: Aleksandar Rikalo Message-Id: <1551800076-8104-8-git-send-email-aleksandar.markovic@rt-rk.com> --- tests/tcg/mips/include/wrappers_msa.h | 51 +++++++++++++++++++++++++++++++++++ 1 file changed, 51 insertions(+) diff --git a/tests/tcg/mips/include/wrappers_msa.h b/tests/tcg/mips/include/wrappers_msa.h index c650ed2..9cffd55 100644 --- a/tests/tcg/mips/include/wrappers_msa.h +++ b/tests/tcg/mips/include/wrappers_msa.h @@ -38,6 +38,21 @@ static inline void do_msa_##suffix(void *input, void *output) \ ); \ } +#define DO_MSA__WD__WD(suffix, mnemonic) \ +static inline void do_msa_##suffix(void *input, void *output) \ +{ \ + __asm__ volatile ( \ + "move $t0, %0\n\t" \ + "ld.d $w11, 0($t0)\n\t" \ + #mnemonic " $w10, $w10\n\t" \ + "move $t0, %1\n\t" \ + "st.d $w10, 0($t0)\n\t" \ + : \ + : "r" (input), "r" (output) \ + : "t0", "memory" \ + ); \ +} + DO_MSA__WD__WS(NLOC_B, nloc.b) DO_MSA__WD__WS(NLOC_H, nloc.h) DO_MSA__WD__WS(NLOC_W, nloc.w) @@ -72,6 +87,42 @@ static inline void do_msa_##suffix(void *input1, void *input2, \ ); \ } +#define DO_MSA__WD__WD_WT(suffix, mnemonic) \ +static inline void do_msa_##suffix(void *input1, void *input2, \ + void *output) \ +{ \ + __asm__ volatile ( \ + "move $t0, %0\n\t" \ + "ld.d $w11, 0($t0)\n\t" \ + "move $t0, %1\n\t" \ + "ld.d $w12, 0($t0)\n\t" \ + #mnemonic " $w10, $w10, $w12\n\t" \ + "move $t0, %2\n\t" \ + "st.d $w10, 0($t0)\n\t" \ + : \ + : "r" (input1), "r" (input2), "r" (output) \ + : "t0", "memory" \ + ); \ +} + +#define DO_MSA__WD__WS_WD(suffix, mnemonic) \ +static inline void do_msa_##suffix(void *input1, void *input2, \ + void *output) \ +{ \ + __asm__ volatile ( \ + "move $t0, %0\n\t" \ + "ld.d $w11, 0($t0)\n\t" \ + "move $t0, %1\n\t" \ + "ld.d $w12, 0($t0)\n\t" \ + #mnemonic " $w10, $w11, $w10\n\t" \ + "move $t0, %2\n\t" \ + "st.d $w10, 0($t0)\n\t" \ + : \ + : "r" (input1), "r" (input2), "r" (output) \ + : "t0", "memory" \ + ); \ +} + DO_MSA__WD__WS_WT(ILVEV_B, ilvev.b) DO_MSA__WD__WS_WT(ILVEV_H, ilvev.h) DO_MSA__WD__WS_WT(ILVEV_W, ilvev.w)