From patchwork Tue Mar 5 15:34:24 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Aleksandar Markovic X-Patchwork-Id: 1051788 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=rt-rk.com Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 44DLfy6tX2z9s4Y for ; Wed, 6 Mar 2019 02:39:37 +1100 (AEDT) Received: from localhost ([127.0.0.1]:44666 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1h1CAH-0005LA-UF for incoming@patchwork.ozlabs.org; Tue, 05 Mar 2019 10:39:34 -0500 Received: from eggs.gnu.org ([209.51.188.92]:35377) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1h1C64-0002ON-Vv for qemu-devel@nongnu.org; Tue, 05 Mar 2019 10:35:14 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1h1C63-0002pA-EW for qemu-devel@nongnu.org; Tue, 05 Mar 2019 10:35:12 -0500 Received: from mx2.rt-rk.com ([89.216.37.149]:54174 helo=mail.rt-rk.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1h1C62-0002BZ-Vo for qemu-devel@nongnu.org; Tue, 05 Mar 2019 10:35:11 -0500 Received: from localhost (localhost [127.0.0.1]) by mail.rt-rk.com (Postfix) with ESMTP id 5ADFE1A2216; Tue, 5 Mar 2019 16:35:02 +0100 (CET) X-Virus-Scanned: amavisd-new at rt-rk.com Received: from rtrkw774-lin.domain.local (rtrkw774-lin.domain.local [10.10.13.43]) by mail.rt-rk.com (Postfix) with ESMTPSA id 3C7FC1A21FB; Tue, 5 Mar 2019 16:35:02 +0100 (CET) From: Aleksandar Markovic To: qemu-devel@nongnu.org Date: Tue, 5 Mar 2019 16:34:24 +0100 Message-Id: <1551800076-8104-3-git-send-email-aleksandar.markovic@rt-rk.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1551800076-8104-1-git-send-email-aleksandar.markovic@rt-rk.com> References: <1551800076-8104-1-git-send-email-aleksandar.markovic@rt-rk.com> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x X-Received-From: 89.216.37.149 Subject: [Qemu-devel] [PATCH v8 02/14] disas: nanoMIPS: Add graphical description of pool organization X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: arikalo@wavecomp.com, amarkovic@wavecomp.com, aurelien@aurel32.net Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" From: Aleksandar Markovic Add graphical description of nanoMIPS instruction pool organization. Signed-off-by: Aleksandar Markovic Reviewed-by: Aleksandar Rikalo --- disas/nanomips.cpp | 102 +++++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 102 insertions(+) diff --git a/disas/nanomips.cpp b/disas/nanomips.cpp index 1491379..c8495b1 100644 --- a/disas/nanomips.cpp +++ b/disas/nanomips.cpp @@ -16603,6 +16603,108 @@ std::string NMD::YIELD(uint64 instruction) +/* + * nanoMIPS instruction pool organization + * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + * + * + * ┌─ P.ADDIU ─── P.RI ─── P.SYSCALL + * │ + * │ ┌─ P.TRAP + * │ │ + * │ ┌─ _POOL32A0_0 ─┼─ P.CMOVE + * │ │ │ + * │ │ └─ P.SLTU + * │ ┌─ _POOL32A0 ─┤ + * │ │ │ + * │ │ │ + * │ │ └─ _POOL32A0_1 ─── CRC32 + * │ │ + * ├─ P32A ─┤ + * │ │ ┌─ PP.LSX + * │ │ ┌─ P.LSX ─────┤ + * │ │ │ └─ PP.LSXS + * │ └─ _POOL32A7 ─┤ + * │ │ ┌─ POOL32Axf_4 + * │ └─ POOL32Axf ─┤ + * │ └─ POOL32Axf_5 + * │ + * ├─ PBAL + * │ + * ├─ P.GP.W ┌─ PP.LSX + * ┌─ P32 ─┤ │ + * │ ├─ P.GP.BH ─┴─ PP.LSXS + * │ │ + * │ ├─ P.J ─────── PP.BALRSC + * │ │ + * │ ├─ P48I + * │ │ ┌─ P.SR + * │ │ │ + * │ │ ├─ P.SHIFT + * │ │ │ + * │ ├─ P.U12 ───┼─ P.ROTX + * │ │ │ + * │ │ ├─ P.INS + * │ │ │ + * │ │ └─ P.EXT + * │ │ + * │ ├─ P.LS.U12 ── P.PREF.U12 + * │ │ + * │ ├─ P.BR1 ───── P.BR3A + * │ │ + * │ │ ┌─ P.LS.S0 ─── P16.SYSCALL + * │ │ │ + * │ │ │ ┌─ P.LL + * │ │ ├─ P.LS.S1 ─┤ + * │ │ │ └─ P.SC + * │ │ │ + * │ │ │ ┌─ P.PREFE + * MAJOR ─┤ ├─ P.LS.S9 ─┤ │ + * │ │ ├─ P.LS.E0 ─┼─ P.LLE + * │ │ │ │ + * │ │ │ └─ P.SCE + * │ │ │ + * │ │ ├─ P.LS.WM + * │ │ │ + * │ │ └─ P.LS.UAWM + * │ │ + * │ │ + * │ ├─ P.BR2 + * │ │ + * │ ├─ P.BRI + * │ │ + * │ └─ P.LUI + * │ + * │ + * │ ┌─ P16.MV ──── P16.RI ─── P16.SYSCALL + * │ │ + * │ ├─ P16.SR + * │ │ + * │ ├─ P16.SHIFT + * │ │ + * │ ├─ P16.4x4 + * │ │ + * │ ├─ P16C ────── POOL16C_0 ── POOL16C_00 + * │ │ + * └─ P16 ─┼─ P16.LB + * │ + * ├─ P16.A1 + * │ + * ├─ P16.LH + * │ + * ├─ P16.A2 ──── P.ADDIU[RS5] + * │ + * ├─ P16.ADDU + * │ + * └─ P16.BR ──┬─ P16.JRC + * │ + * └─ P16.BR1 + * + * + * (FP, DPS, and some minor instruction pools are omitted from the diagram) + * + */ + NMD::Pool NMD::P_SYSCALL[2] = { { instruction , 0 , 0 , 32, 0xfffc0000, 0x00080000, &NMD::SYSCALL_32_ , 0,