[PULL,v2,10/12] target/mips: Add CP0 register MemoryMapID

Message ID	1547830785-7079-11-git-send-email-aleksandar.markovic@rt-rk.com
State	New
Headers	show Return-Path: <qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org> From: Aleksandar Markovic <aleksandar.markovic@rt-rk.com> To: qemu-devel@nongnu.org Date: Fri, 18 Jan 2019 17:59:43 +0100 Message-Id: <1547830785-7079-11-git-send-email-aleksandar.markovic@rt-rk.com> In-Reply-To: <1547830785-7079-1-git-send-email-aleksandar.markovic@rt-rk.com> References: <1547830785-7079-1-git-send-email-aleksandar.markovic@rt-rk.com> Subject: [Qemu-devel] [PULL v2 10/12] target/mips: Add CP0 register MemoryMapID Precedence: list Cc: peter.maydell@linaro.org, amarkovic@wavecomp.com Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" <qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>
Series	[PULL,v2,01/12] target/mips: Move comment containing summary of CP0 registers \| expand [PULL,v2,01/12] target/mips: Move comment containing summary of CP0 registers [PULL,v2,02/12] target/mips: Add preprocessor constants for 32 major CP0 registers [PULL,v2,03/12] target/mips: Use preprocessor constants for 32 major CP0 registers [PULL,v2,04/12] target/mips: Add fields for SAARI and SAAR CP0 registers [PULL,v2,05/12] target/mips: Provide R/W access to SAARI and SAAR CP0 registers [PULL,v2,06/12] target/mips: Add field and R/W access to ITU control register ICR0 [PULL,v2,07/12] target/mips: Update ITU to utilize SAARI and SAAR CP0 registers [PULL,v2,08/12] target/mips: Update ITU to handle bus errors [PULL,v2,09/12] target/mips: Amend preprocessor constants for CP0 registers [PULL,v2,10/12] target/mips: Add CP0 register MemoryMapID [PULL,v2,11/12] target/mips: Rename 'rn' to 'register_name' [PULL,v2,12/12] target/mips: Introduce 32 R5900 multimedia registers

Message ID

1547830785-7079-11-git-send-email-aleksandar.markovic@rt-rk.com

State

New

Headers

From: Aleksandar Markovic <aleksandar.markovic@rt-rk.com>
To: qemu-devel@nongnu.org
Date: Fri, 18 Jan 2019 17:59:43 +0100
Message-Id: <1547830785-7079-11-git-send-email-aleksandar.markovic@rt-rk.com>
In-Reply-To: <1547830785-7079-1-git-send-email-aleksandar.markovic@rt-rk.com>
References: <1547830785-7079-1-git-send-email-aleksandar.markovic@rt-rk.com>
Subject: [Qemu-devel] [PULL v2 10/12] target/mips: Add CP0 register
	MemoryMapID
Precedence: list
Cc: peter.maydell@linaro.org, amarkovic@wavecomp.com
Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org
Sender: "Qemu-devel"
	<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>

Series

[PULL,v2,01/12] target/mips: Move comment containing summary of CP0 registers | expand

Commit Message

Aleksandar Markovic Jan. 18, 2019, 4:59 p.m. UTC

From: Aleksandar Markovic <amarkovic@wavecomp.com>

Add CP0 register MemoryMapID. Only data field is added.
The corresponding functionality will be added in future
patches.

Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
---
 target/mips/cpu.h     | 1 +
 target/mips/machine.c | 5 +++--
 2 files changed, 4 insertions(+), 2 deletions(-)

diff --git a/target/mips/cpu.h b/target/mips/cpu.h
index a5381b7..21daf50 100644
--- a/target/mips/cpu.h
+++ b/target/mips/cpu.h
@@ -536,6 +536,7 @@  struct CPUMIPSState {
  */
     target_ulong CP0_Context;
     target_ulong CP0_KScratch[MIPS_KSCRATCH_NUM];
+    int32_t CP0_MemoryMapID;
 /*
  * CP0 Register 5
  */
diff --git a/target/mips/machine.c b/target/mips/machine.c
index 111d7c3..1341ab1 100644
--- a/target/mips/machine.c
+++ b/target/mips/machine.c
@@ -214,8 +214,8 @@  const VMStateDescription vmstate_tlb = {
 
 const VMStateDescription vmstate_mips_cpu = {
     .name = "cpu",
-    .version_id = 16,
-    .minimum_version_id = 16,
+    .version_id = 17,
+    .minimum_version_id = 17,
     .post_load = cpu_post_load,
     .fields = (VMStateField[]) {
         /* Active TC */
@@ -253,6 +253,7 @@  const VMStateDescription vmstate_mips_cpu = {
         VMSTATE_UINT64(env.CP0_EntryLo0, MIPSCPU),
         VMSTATE_UINT64(env.CP0_EntryLo1, MIPSCPU),
         VMSTATE_UINTTL(env.CP0_Context, MIPSCPU),
+        VMSTATE_INT32(env.CP0_MemoryMapID, MIPSCPU),
         VMSTATE_INT32(env.CP0_PageMask, MIPSCPU),
         VMSTATE_INT32(env.CP0_PageGrain, MIPSCPU),
         VMSTATE_UINTTL(env.CP0_SegCtl0, MIPSCPU),

[PULL,v2,10/12] target/mips: Add CP0 register MemoryMapID

Commit Message

Patch