| Message ID | 1542202628-6538-1-git-send-email-stefan.markovic@rt-rk.com |
|---|---|
| State | New |
| Headers | show |
| Series | linux-user: Update MIPS specific prctl() implementation | expand |
On 14/11/2018 14:37, Stefan Markovic wrote: > From: Stefan Markovic <smarkovic@wavecomp.com> > > Perform needed checks before actual prctl() PR_SET_FP_MODE and > PR_GET_FP_MODE work based on kernel implementation. Also, update > necessary hflags. > > Signed-off-by: Stefan Markovic <smarkovic@wavecomp.com> I think it's better if you send the patch with the email address of the S-o-b. > --- > linux-user/syscall.c | 18 ++++++++++++++++++ > 1 file changed, 18 insertions(+) > Reviewed-by: Laurent Vivier <laurent@vivier.eu> If you plan to do a MIPS p-r before the next RC, don't hesitate to add this patch to it (my linux-user queue is empty for the moment). Thanks, Laurent
From: Laurent Vivier <laurent@vivier.eu> > Reviewed-by: Laurent Vivier <laurent@vivier.eu> > > If you plan to do a MIPS p-r before the next RC, don't hesitate to add > this patch to it (my linux-user queue is empty for the moment). Laurent, I plan to create a MIPS pull request in next few days, and I am going to include this patch in it (unless you tell me not to do so). Thanks a bunch!! Aleksandar
diff --git a/linux-user/syscall.c b/linux-user/syscall.c index 810a58b..10db8b7 100644 --- a/linux-user/syscall.c +++ b/linux-user/syscall.c @@ -9544,9 +9544,25 @@ static abi_long do_syscall1(void *cpu_env, int num, abi_long arg1, { CPUMIPSState *env = ((CPUMIPSState *)cpu_env); bool old_fr = env->CP0_Status & (1 << CP0St_FR); + bool old_fre = env->CP0_Config5 & (1 << CP0C5_FRE); bool new_fr = arg2 & TARGET_PR_FP_MODE_FR; bool new_fre = arg2 & TARGET_PR_FP_MODE_FRE; + const unsigned int known_bits = TARGET_PR_FP_MODE_FR | + TARGET_PR_FP_MODE_FRE; + + /* If nothing to change, return right away, successfully. */ + if (old_fr == new_fr && old_fre == new_fre) { + return 0; + } + /* Check the value is valid */ + if (arg2 & ~known_bits) { + return -TARGET_EOPNOTSUPP; + } + /* Setting FRE without FR is not supported. */ + if (new_fre && !new_fr) { + return -TARGET_EOPNOTSUPP; + } if (new_fr && !(env->active_fpu.fcr0 & (1 << FCR0_F64))) { /* FR1 is not supported */ return -TARGET_EOPNOTSUPP; @@ -9576,6 +9592,7 @@ static abi_long do_syscall1(void *cpu_env, int num, abi_long arg1, env->hflags |= MIPS_HFLAG_F64; } else { env->CP0_Status &= ~(1 << CP0St_FR); + env->hflags &= ~MIPS_HFLAG_F64; } if (new_fre) { env->CP0_Config5 |= (1 << CP0C5_FRE); @@ -9584,6 +9601,7 @@ static abi_long do_syscall1(void *cpu_env, int num, abi_long arg1, } } else { env->CP0_Config5 &= ~(1 << CP0C5_FRE); + env->hflags &= ~MIPS_HFLAG_FRE; } return 0;