diff mbox series

[v6,02/18] target/mips: Define a bit for MXU in insn_flags

Message ID	1540311509-23970-3-git-send-email-aleksandar.markovic@rt-rk.com
State	New
Headers	show Return-Path: <qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org> From: Aleksandar Markovic <aleksandar.markovic@rt-rk.com> To: qemu-devel@nongnu.org Date: Tue, 23 Oct 2018 18:18:13 +0200 Message-Id: <1540311509-23970-3-git-send-email-aleksandar.markovic@rt-rk.com> In-Reply-To: <1540311509-23970-1-git-send-email-aleksandar.markovic@rt-rk.com> References: <1540311509-23970-1-git-send-email-aleksandar.markovic@rt-rk.com> Subject: [Qemu-devel] [PATCH v6 02/18] target/mips: Define a bit for MXU in insn_flags Precedence: list Cc: jancraig@amazon.com, smarkovic@wavecomp.com, richard.henderson@linaro.org, amarkovic@wavecomp.com, pjovanovic@wavecomp.com, aurelien@aurel32.net Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" <qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>
Series	target/mips: Add limited support for Ingenic's MXU ASE \| expand [v6,00/18] target/mips: Add limited support for Ingenic's MXU ASE [v6,01/18] target/mips: Introduce MXU registers [v6,02/18] target/mips: Define a bit for MXU in insn_flags [v6,03/18] target/mips: Amend MXU instruction opcodes [v6,04/18] target/mips: Add and integrate MXU decoding engine placeholder [v6,05/18] target/mips: Add MXU decoding engine [v6,06/18] target/mips: Add bit encoding for MXU accumulate add/sub 1-bit pattern 'aptn1' [v6,07/18] target/mips: Add bit encoding for MXU accumulate add/sub 2-bit pattern 'aptn2' [v6,08/18] target/mips: Add bit encoding for MXU execute add/sub pattern 'eptn2' [v6,09/18] target/mips: Add bit encoding for MXU operand getting pattern 'optn2' [v6,10/18] target/mips: Add bit encoding for MXU operand getting pattern 'optn3' [v6,11/18] target/mips: Add emulation of non-MXU MULL within MXU decoding engine [v6,12/18] target/mips: Add emulation of MXU instructions S32I2M and S32M2I [v6,13/18] target/mips: Move MUL, S32M2I, S32I2M handling out of main MXU switch [v6,14/18] target/mips: Add emulation of MXU instruction S8LDD [v6,15/18] target/mips: Add emulation of MXU instruction D16MUL [v6,16/18] target/mips: Add emulation of MXU instruction D16MAC [v6,17/18] target/mips: Add emulation of MXU instructions Q8MUL and Q8MULSU [v6,18/18] target/mips: Add emulation of MXU instructions S32LDD and S32LDDR

Commit Message

Aleksandar Markovic Oct. 23, 2018, 4:18 p.m. UTC

From: Craig Janeczek <jancraig@amazon.com>

Define a bit for MXU in insn_flags. This is the first non-MIPS
(third party) ASE supported in QEMU for MIPS, so it is placed in
the section "bits 56-63: vendor-specific ASEs".

Signed-off-by: Craig Janeczek <jancraig@amazon.com>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
---
 target/mips/mips-defs.h | 1 +
 1 file changed, 1 insertion(+)

diff mbox series

Patch

diff --git a/target/mips/mips-defs.h b/target/mips/mips-defs.h
index 5177618..dbdb4b2 100644
--- a/target/mips/mips-defs.h
+++ b/target/mips/mips-defs.h
@@ -69,6 +69,7 @@ 
  *   bits 56-63: vendor-specific ASEs
  */
 #define ASE_MMI           0x0100000000000000ULL
+#define ASE_MXU           0x0200000000000000ULL
 
 /* MIPS CPU defines. */
 #define		CPU_MIPS1	(ISA_MIPS1)