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[v6,10/18] target/mips: Add bit encoding for MXU operand getting pattern 'optn3'

Message ID 1540311509-23970-11-git-send-email-aleksandar.markovic@rt-rk.com
State New
Headers show
Series target/mips: Add limited support for Ingenic's MXU ASE | expand

Commit Message

Aleksandar Markovic Oct. 23, 2018, 4:18 p.m. UTC 
From: Craig Janeczek <jancraig@amazon.com>

Add bit encoding for MXU operand getting pattern 'optn3'.

Signed-off-by: Craig Janeczek <jancraig@amazon.com>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
---
 target/mips/translate.c | 10 ++++++++++
 1 file changed, 10 insertions(+)
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Patch

diff --git a/target/mips/translate.c b/target/mips/translate.c
index f3e87ce..5bcf6a4 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -23867,6 +23867,16 @@  static void decode_opc_special(CPUMIPSState *env, DisasContext *ctx)
 #define MXU_OPTN2_HW    2
 #define MXU_OPTN2_XW    3
 
+/* MXU operand getting pattern 'optn3' */
+#define MXU_OPTN3_PTN0  0
+#define MXU_OPTN3_PTN1  1
+#define MXU_OPTN3_PTN2  2
+#define MXU_OPTN3_PTN3  3
+#define MXU_OPTN3_PTN4  4
+#define MXU_OPTN3_PTN5  5
+#define MXU_OPTN3_PTN6  6
+#define MXU_OPTN3_PTN7  7
+
 
 /*
  *