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[PULL,33/34] target/mips: Fix the title of translate.c

Message ID	1540213077-15211-34-git-send-email-aleksandar.markovic@rt-rk.com
State	New
Headers	show Return-Path: <qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org> From: Aleksandar Markovic <aleksandar.markovic@rt-rk.com> To: qemu-devel@nongnu.org Date: Mon, 22 Oct 2018 14:57:56 +0200 Message-Id: <1540213077-15211-34-git-send-email-aleksandar.markovic@rt-rk.com> In-Reply-To: <1540213077-15211-1-git-send-email-aleksandar.markovic@rt-rk.com> References: <1540213077-15211-1-git-send-email-aleksandar.markovic@rt-rk.com> Subject: [Qemu-devel] [PULL 33/34] target/mips: Fix the title of translate.c Precedence: list Cc: peter.maydell@linaro.org, amarkovic@wavecomp.com Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" <qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>
Series	[PULL,01/34] target/mips: Define R5900 ISA, MMI ASE, and R5900 CPU preprocessor constants \| expand [PULL,01/34] target/mips: Define R5900 ISA, MMI ASE, and R5900 CPU preprocessor constants [PULL,02/34] disas/mips: Define R5900 disassembly constants [PULL,03/34] target/mips: R5900 Multimedia Instruction overview note [PULL,04/34] target/mips: Define R5900 MMI class, and LQ and SQ opcode constants [PULL,05/34] target/mips: Define R5900 MMI{0, 1, 2, 3} subclasses and MMI opcode constants [PULL,06/34] target/mips: Define R5900 MMI0 opcode constants [PULL,07/34] target/mips: Define R5900 MMI1 opcode constants [PULL,08/34] target/mips: Define R5900 MMI2 opcode constants [PULL,09/34] target/mips: Define R5900 MMI3 opcode constants [PULL,10/34] target/mips: Placeholder for R5900 SQ, handle user mode RDHWR [PULL,11/34] target/mips: Placeholder for R5900 LQ [PULL,12/34] target/mips: Placeholder for R5900 MMI instruction class [PULL,13/34] target/mips: Placeholder for R5900 MMI0 instruction subclass [PULL,14/34] target/mips: Placeholder for R5900 MMI1 instruction subclass [PULL,15/34] target/mips: Placeholder for R5900 MMI2 instruction subclass [PULL,16/34] target/mips: Placeholder for R5900 MMI3 instruction subclass [PULL,17/34] target/mips: Support R5900 three-operand MULT and MULTU instructions [PULL,18/34] target/mips: Support R5900 three-operand MULT1 and MULTU1 instructions [PULL,19/34] target/mips: Support R5900 MFLO1, MTLO1, MFHI1 and MTHI1 instructions [PULL,20/34] target/mips: Support R5900 DIV1 and DIVU1 instructions [PULL,21/34] target/mips: Support R5900 MOVN, MOVZ and PREF instructions from MIPS IV [PULL,22/34] target/mips: R5900 DMULT[U], DDIV[U], LL[D] and SC[D] are user only [PULL,23/34] tests/tcg/mips: Test R5900 three-operand MULT [PULL,24/34] tests/tcg/mips: Test R5900 three-operand MULTU [PULL,25/34] tests/tcg/mips: Test R5900 three-operand MULT1 [PULL,26/34] tests/tcg/mips: Test R5900 three-operand MULTU1 [PULL,27/34] tests/tcg/mips: Test R5900 MFLO1 and MFHI1 [PULL,28/34] tests/tcg/mips: Test R5900 MTLO1 and MTHI1 [PULL,29/34] tests/tcg/mips: Test R5900 DIV1 [PULL,30/34] tests/tcg/mips: Test R5900 DIVU1 [PULL,31/34] target/mips: Define the R5900 CPU [PULL,32/34] linux-user/mips: Recognise the R5900 CPU model [PULL,33/34] target/mips: Fix the title of translate.c [PULL,34/34] target/mips: Fix decoding of ALIGN and DALIGN instructions

Commit Message

Aleksandar Markovic Oct. 22, 2018, 12:57 p.m. UTC

From: Aleksandar Markovic <amarkovic@wavecomp.com>

Replace MIPS32 with MIPS, since the file covers all generations
of MIPS architectures.

Reviewed-by: Stefan Markovic <smarkovic@wavecomp.com>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
---
 target/mips/translate.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff mbox series

Patch

diff --git a/target/mips/translate.c b/target/mips/translate.c
index 6c50485..4db21b3 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -1,5 +1,5 @@ 
 /*
- *  MIPS32 emulation for qemu: main translation routines.
+ *  MIPS emulation for QEMU: main translation routines.
  *
  *  Copyright (c) 2004-2005 Jocelyn Mayer
  *  Copyright (c) 2006 Marius Groeger (FPU operations)