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[PULL,v2,01/28] mailmap: Add an item for Yongbok Kim

Message ID	1539888473-16340-2-git-send-email-aleksandar.markovic@rt-rk.com
State	New
Headers	show Return-Path: <qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org> From: Aleksandar Markovic <aleksandar.markovic@rt-rk.com> To: qemu-devel@nongnu.org Date: Thu, 18 Oct 2018 20:47:26 +0200 Message-Id: <1539888473-16340-2-git-send-email-aleksandar.markovic@rt-rk.com> In-Reply-To: <1539888473-16340-1-git-send-email-aleksandar.markovic@rt-rk.com> References: <1539888473-16340-1-git-send-email-aleksandar.markovic@rt-rk.com> Subject: [Qemu-devel] [PULL v2 01/28] mailmap: Add an item for Yongbok Kim Precedence: list Cc: peter.maydell@linaro.org, amarkovic@wavecomp.com Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" <qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>
Series	[PULL,v2,01/28] mailmap: Add an item for Yongbok Kim \| expand [PULL,v2,01/28] mailmap: Add an item for Yongbok Kim [PULL,v2,02/28] elf: Fix PT_MIPS_XXX constants [PULL,v2,03/28] elf: Add MIPS_ABI_FP_XXX constants [PULL,v2,04/28] elf: Add Mips_elf_abiflags_v0 structure [PULL,v2,06/28] linux-user: Add MIPS-specific prctl() options [PULL,v2,07/28] linux-user: Add infrastructure for handling MIPS-specific prctl() [PULL,v2,08/28] target/mips: Add a comment with an overview of CP0 registers [PULL,v2,09/28] target/mips: Add a comment before each CP0 register section in cpu.h [PULL,v2,10/28] target/mips: Add basic description of MXU ASE [PULL,v2,11/28] target/mips: Add assembler mnemonics list for MXU ASE [PULL,v2,12/28] target/mips: Add organizational chart of MXU ASE [PULL,v2,13/28] target/mips: Add opcode values of MXU ASE [PULL,v2,14/28] target/mips: Increase 'supported ISAs/ASEs' flag holder size [PULL,v2,15/28] target/mips: Reorganize bit definitions for insn_flags (ISAs/ASEs flags) [PULL,v2,16/28] target/mips: Add bit definitions for DSP R3 ASE [PULL,v2,17/28] target/mips: Add availability control for DSP R3 ASE [PULL,v2,18/28] target/mips: Improve DSP R2/R3-related naming [PULL,v2,19/28] target/mips: Add CP0 Config2 to DisasContext [PULL,v2,20/28] target/mips: Add CP0 PWBase register [PULL,v2,21/28] target/mips: Add CP0 PWField register [PULL,v2,22/28] target/mips: Add CP0 PWSize register [PULL,v2,23/28] target/mips: Add CP0 PWCtl register [PULL,v2,24/28] target/mips: Add reset state for PWSize and PWField registers [PULL,v2,25/28] target/mips: Implement hardware page table walker for MIPS32 [PULL,v2,26/28] target/mips: Fix emulation of microMIPS R6 <SELEQZ\|SELNEZ>.<D\|S> [PULL,v2,27/28] target/mips: Fix misplaced 'break' in handling of NM_SHRA_R_PH [PULL,v2,28/28] target/mips: Add opcodes for nanoMIPS EVA instructions

Commit Message

Aleksandar Markovic Oct. 18, 2018, 6:47 p.m. UTC

From: Aleksandar Markovic <amarkovic@wavecomp.com>

Yongbok Kim used two email adresses for QEMU contributions -
his company changed its ownership/name.

Reviewed-by: Stefan Markovic <smarkovic@wavecomp.com>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
---
 .mailmap | 1 +
 1 file changed, 1 insertion(+)

diff mbox series

Patch

diff --git a/.mailmap b/.mailmap
index 6f2ff22..ed8faa5 100644
--- a/.mailmap
+++ b/.mailmap
@@ -12,6 +12,7 @@  Fabrice Bellard <fabrice@bellard.org> bellard <bellard@c046a42c-6fe2-441c-8c8c-7
 James Hogan <jhogan@kernel.org> <james.hogan@imgtec.com>
 Jocelyn Mayer <l_indien@magic.fr> j_mayer <j_mayer@c046a42c-6fe2-441c-8c8c-71466251a162>
 Paul Brook <paul@codesourcery.com> pbrook <pbrook@c046a42c-6fe2-441c-8c8c-71466251a162>
+Yongbok Kim <yongbok.kim@mips.com> <yongbok.kim@imgtec.com>
 Aleksandar Markovic <amarkovic@wavecomp.com> <aleksandar.markovic@mips.com>
 Aleksandar Markovic <amarkovic@wavecomp.com> <aleksandar.markovic@imgtec.com>
 Paul Burton <pburton@wavecomp.com> <paul.burton@mips.com>