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[PULL,v2,10/28] target/mips: Add basic description of MXU ASE

Message ID 1539888473-16340-11-git-send-email-aleksandar.markovic@rt-rk.com
State New
Headers show
Series [PULL,v2,01/28] mailmap: Add an item for Yongbok Kim | expand

Commit Message

Aleksandar Markovic Oct. 18, 2018, 6:47 p.m. UTC 
From: Aleksandar Markovic <amarkovic@wavecomp.com>

Add a comment that contains a basic description of MXU ASE.

Reviewed-by: Stefan Markovic <smarkovic@wavecomp.com>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
---
 target/mips/translate.c | 20 ++++++++++++++++++++
 1 file changed, 20 insertions(+)
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Patch

diff --git a/target/mips/translate.c b/target/mips/translate.c
index ab16cdb..46655bb 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -1389,6 +1389,26 @@  enum {
     OPC_BINSRI_df   = (0x7 << 23) | OPC_MSA_BIT_09,
 };
 
+
+/*
+ *    AN OVERVIEW OF MXU EXTENSION INSTRUCTION SET
+ *    ============================================
+ *
+ * MXU (full name: MIPS eXtension/enhanced Unit) is an SIMD extension of MIPS32
+ * instructions set. It is designed to fit the needs of signal, graphical and
+ * video processing applications. MXU instruction set is used in Xburst family
+ * of microprocessors by Ingenic.
+ *
+ * MXU unit contains 17 registers called X0-X16. X0 is always zero, and X16 is
+ * the control register.
+ *
+ *   Compiled after:
+ *
+ *   "XBurst® Instruction Set Architecture MIPS eXtension/enhanced Unit
+ *   Programming Manual", Ingenic Semiconductor Co, Ltd., 2017
+ */
+
+
 /* global register indices */
 static TCGv cpu_gpr[32], cpu_PC;
 static TCGv cpu_HI[MIPS_DSP_ACC], cpu_LO[MIPS_DSP_ACC];