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[v11,24/46] target/mips: Add CP0 Config3 and Config5 fields to DisasContext structure

Message ID 1534789014-8310-25-git-send-email-aleksandar.markovic@rt-rk.com
State New
Headers show
Series Add nanoMIPS support - core functionality and system mode | expand

Commit Message

Aleksandar Markovic Aug. 20, 2018, 6:16 p.m. UTC 
From: Dimitrije Nikolic <dnikolic@wavecomp.com>

Add CP0_Config3 and CP0_Config5 to DisasContext structure. This is
needed for implementing availability control of various instructions.

Signed-off-by: "Aleksandar Markovic <amarkovic@wavecomp.com>"
---
 target/mips/translate.c | 4 ++++
 1 file changed, 4 insertions(+)

Comments

Aleksandar Markovic Aug. 21, 2018, 11:04 a.m. UTC | #1 
> From: Aleksandar Markovic <aleksandar.markovic@rt-rk.com>
> Sent: Monday, August 20, 2018 8:16 PM
> 
> Subject: [PATCH v11 24/46] target/mips: Add CP0 Config3 and Config5 fields to DisasContext structure
> 
> From: Dimitrije Nikolic <dnikolic@wavecomp.com>
> 
> Add CP0_Config3 and CP0_Config5 to DisasContext structure. This is
> needed for implementing availability control of various instructions.
> 
> Signed-off-by: "Aleksandar Markovic <amarkovic@wavecomp.com>"
> ---
> target/mips/translate.c | 4 ++++
> 1 file changed, 4 insertions(+)

Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com>
diff mbox series

Patch

diff --git a/target/mips/translate.c b/target/mips/translate.c
index 076f4bf..f0c50cb 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -1449,6 +1449,8 @@  typedef struct DisasContext {
     uint32_t opcode;
     int insn_flags;
     int32_t CP0_Config1;
+    int32_t CP0_Config3;
+    int32_t CP0_Config5;
     /* Routine used to access memory */
     int mem_idx;
     TCGMemOp default_tcg_memop_mask;
@@ -23305,6 +23307,8 @@  static void mips_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
     ctx->saved_pc = -1;
     ctx->insn_flags = env->insn_flags;
     ctx->CP0_Config1 = env->CP0_Config1;
+    ctx->CP0_Config3 = env->CP0_Config3;
+    ctx->CP0_Config5 = env->CP0_Config5;
     ctx->btarget = 0;
     ctx->kscrexist = (env->CP0_Config4 >> CP0C4_KScrExist) & 0xff;
     ctx->rxi = (env->CP0_Config3 >> CP0C3_RXI) & 1;