@@ -16586,6 +16586,19 @@ enum {
NM_EVP = 0x01,
};
+
+/*
+ *
+ * nanoMIPS decoding engine
+ *
+ */
+
+static int decode_nanomips_opc(CPUMIPSState *env, DisasContext *ctx)
+{
+ return 2;
+}
+
+
/* SmartMIPS extension to MIPS32 */
#if defined(TARGET_MIPS64)
@@ -21402,7 +21415,10 @@ static void mips_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs)
int is_slot;
is_slot = ctx->hflags & MIPS_HFLAG_BMASK;
- if (!(ctx->hflags & MIPS_HFLAG_M16)) {
+ if (ctx->insn_flags & ISA_NANOMIPS32) {
+ ctx->opcode = cpu_lduw_code(env, ctx->base.pc_next);
+ insn_bytes = decode_nanomips_opc(env, ctx);
+ } else if (!(ctx->hflags & MIPS_HFLAG_M16)) {
ctx->opcode = cpu_ldl_code(env, ctx->base.pc_next);
insn_bytes = 4;
decode_opc(env, ctx);
@@ -21841,8 +21857,8 @@ void cpu_state_reset(CPUMIPSState *env)
env->CP0_Status |= (1 << CP0St_FR);
}
- if (env->CP0_Config3 & (1 << CP0C3_ISA)) {
- /* microMIPS on reset when Config3.ISA == {1, 3} */
+ if (env->CP0_Config3 & (1 << (CP0C3_ISA + 1))) {
+ /* microMIPS on reset when Config3.ISA == 3 */
env->hflags |= MIPS_HFLAG_M16;
}