From patchwork Thu Aug 9 11:53:29 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Robert Hoo X-Patchwork-Id: 955500 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=2001:4830:134:3::11; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=linux.intel.com Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 41mRyb1VpGz9ryt for ; Thu, 9 Aug 2018 22:14:47 +1000 (AEST) Received: from localhost ([::1]:50160 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fnjq0-0004aa-Q1 for incoming@patchwork.ozlabs.org; Thu, 09 Aug 2018 08:14:44 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:58048) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fnjVd-0001cT-2q for qemu-devel@nongnu.org; Thu, 09 Aug 2018 07:53:42 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fnjVb-00020W-4L for qemu-devel@nongnu.org; Thu, 09 Aug 2018 07:53:40 -0400 Received: from mga02.intel.com ([134.134.136.20]:34246) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1fnjVa-0001xT-Ol for qemu-devel@nongnu.org; Thu, 09 Aug 2018 07:53:39 -0400 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga005.jf.intel.com ([10.7.209.41]) by orsmga101.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 09 Aug 2018 04:53:38 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.53,215,1531810800"; d="scan'208";a="247452665" Received: from sqa-gate.sh.intel.com (HELO robert-ivt.tsp.org) ([10.239.48.212]) by orsmga005.jf.intel.com with ESMTP; 09 Aug 2018 04:53:36 -0700 From: Robert Hoo To: qemu-devel@nongnu.org, pbonzini@redhat.com, rth@twiddle.net, ehabkost@redhat.com, thomas.lendacky@amd.com Date: Thu, 9 Aug 2018 19:53:29 +0800 Message-Id: <1533815609-37245-4-git-send-email-robert.hu@linux.intel.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1533815609-37245-1-git-send-email-robert.hu@linux.intel.com> References: <1533815609-37245-1-git-send-email-robert.hu@linux.intel.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 134.134.136.20 Subject: [Qemu-devel] [PATCH v2 3/3] Change other funcitons referring to feature_word_info[] X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: robert.hu@intel.com, Robert Hoo , jingqi.liu@intel.com Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Add an util function feature_word_description(), which help construct the string describing the feature word (both CPUID and MSR types). report_unavailable_features(): add MSR_FEATURE_WORD type support. x86_cpu_get_feature_words(): limit to CPUID_FEATURE_WORD only. x86_cpu_get_supported_feature_word(): add MSR_FEATURE_WORD type support. x86_cpu_adjust_feat_level(): assert the requested feature must be CPUID_FEATURE_WORD type. Signed-off-by: Robert Hoo --- target/i386/cpu.c | 76 +++++++++++++++++++++++++++++++++++++++++-------------- 1 file changed, 57 insertions(+), 19 deletions(-) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 77e1859..51989e5 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -3024,21 +3024,50 @@ static const TypeInfo host_x86_cpu_type_info = { #endif +/* +*caller should have input str no less than 64 byte length. +*/ +#define FEATURE_WORD_DESCPTION_LEN 64 +static int feature_word_description(char str[], FeatureWordInfo *f, + uint32_t bit) +{ + int ret; + + assert(f->type == CPUID_FEATURE_WORD || + f->type == MSR_FEATURE_WORD); + switch (f->type) { + case CPUID_FEATURE_WORD: + { + const char *reg = get_register_name_32(f->cpuid.reg); + assert(reg); + ret = snprintf(str, FEATURE_WORD_DESCPTION_LEN, + "CPUID.%02XH:%s%s%s [bit %d]", + f->cpuid.eax, reg, + f->feat_names[bit] ? "." : "", + f->feat_names[bit] ? f->feat_names[bit] : "", bit); + break; + } + case MSR_FEATURE_WORD: + ret = snprintf(str, FEATURE_WORD_DESCPTION_LEN, + "MSR(%xH).%s [bit %d]", + f->msr.index, + f->feat_names[bit] ? f->feat_names[bit] : "", bit); + break; + } + return ret > 0; +} + static void report_unavailable_features(FeatureWord w, uint32_t mask) { FeatureWordInfo *f = &feature_word_info[w]; int i; + char feat_word_dscrp_str[FEATURE_WORD_DESCPTION_LEN]; for (i = 0; i < 32; ++i) { if ((1UL << i) & mask) { - const char *reg = get_register_name_32(f->cpuid_reg); - assert(reg); - warn_report("%s doesn't support requested feature: " - "CPUID.%02XH:%s%s%s [bit %d]", + feature_word_description(feat_word_dscrp_str, f, i); + warn_report("%s doesn't support requested feature: %s", accel_uses_host_cpuid() ? "host" : "TCG", - f->cpuid_eax, reg, - f->feat_names[i] ? "." : "", - f->feat_names[i] ? f->feat_names[i] : "", i); + feat_word_dscrp_str); } } } @@ -3276,17 +3305,17 @@ static void x86_cpu_get_feature_words(Object *obj, Visitor *v, { uint32_t *array = (uint32_t *)opaque; FeatureWord w; - X86CPUFeatureWordInfo word_infos[FEATURE_WORDS] = { }; - X86CPUFeatureWordInfoList list_entries[FEATURE_WORDS] = { }; + X86CPUFeatureWordInfo word_infos[FEATURE_WORDS_NUM_CPUID] = { }; + X86CPUFeatureWordInfoList list_entries[FEATURE_WORDS_NUM_CPUID] = { }; X86CPUFeatureWordInfoList *list = NULL; - for (w = 0; w < FEATURE_WORDS; w++) { + for (w = 0; w < FEATURE_WORDS_NUM_CPUID; w++) { FeatureWordInfo *wi = &feature_word_info[w]; X86CPUFeatureWordInfo *qwi = &word_infos[w]; - qwi->cpuid_input_eax = wi->cpuid_eax; - qwi->has_cpuid_input_ecx = wi->cpuid_needs_ecx; - qwi->cpuid_input_ecx = wi->cpuid_ecx; - qwi->cpuid_register = x86_reg_info_32[wi->cpuid_reg].qapi_enum; + qwi->cpuid_input_eax = wi->cpuid.eax; + qwi->has_cpuid_input_ecx = wi->cpuid.needs_ecx; + qwi->cpuid_input_ecx = wi->cpuid.ecx; + qwi->cpuid_register = x86_reg_info_32[wi->cpuid.reg].qapi_enum; qwi->features = array[w]; /* List will be in reverse order, but order shouldn't matter */ @@ -3659,12 +3688,20 @@ static uint32_t x86_cpu_get_supported_feature_word(FeatureWord w, bool migratable_only) { FeatureWordInfo *wi = &feature_word_info[w]; - uint32_t r; + uint32_t r = 0; if (kvm_enabled()) { - r = kvm_arch_get_supported_cpuid(kvm_state, wi->cpuid_eax, - wi->cpuid_ecx, - wi->cpuid_reg); + switch (wi->type) { + case CPUID_FEATURE_WORD: + r = kvm_arch_get_supported_cpuid(kvm_state, wi->cpuid.eax, + wi->cpuid.ecx, + wi->cpuid.reg); + break; + case MSR_FEATURE_WORD: + r = kvm_arch_get_supported_msr_feature(kvm_state, + wi->msr.index); + break; + } } else if (hvf_enabled()) { r = hvf_get_supported_cpuid(wi->cpuid_eax, wi->cpuid_ecx, @@ -4732,9 +4769,10 @@ static void x86_cpu_adjust_feat_level(X86CPU *cpu, FeatureWord w) { CPUX86State *env = &cpu->env; FeatureWordInfo *fi = &feature_word_info[w]; - uint32_t eax = fi->cpuid_eax; + uint32_t eax = fi->cpuid.eax; uint32_t region = eax & 0xF0000000; + assert(feature_word_info[w].type == CPUID_FEATURE_WORD); if (!env->features[w]) { return; }