From patchwork Mon Jul 9 20:50:14 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Aleksandar Markovic X-Patchwork-Id: 941663 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=2001:4830:134:3::11; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=rt-rk.com Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 41PdGM66nWz9rxs for ; Tue, 10 Jul 2018 07:08:11 +1000 (AEST) Received: from localhost ([::1]:44398 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fcdOD-0000tA-EY for incoming@patchwork.ozlabs.org; Mon, 09 Jul 2018 17:08:09 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:54673) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fcd9R-0006Dm-E9 for qemu-devel@nongnu.org; Mon, 09 Jul 2018 16:52:54 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fcd9O-0006Ze-CP for qemu-devel@nongnu.org; Mon, 09 Jul 2018 16:52:53 -0400 Received: from mx2.rt-rk.com ([89.216.37.149]:33404 helo=mail.rt-rk.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1fcd9O-0006ZD-0D for qemu-devel@nongnu.org; Mon, 09 Jul 2018 16:52:50 -0400 Received: from localhost (localhost [127.0.0.1]) by mail.rt-rk.com (Postfix) with ESMTP id A82521A2223; Mon, 9 Jul 2018 22:52:48 +0200 (CEST) X-Virus-Scanned: amavisd-new at rt-rk.com Received: from rtrkw774-lin.mipstec.com (unknown [82.117.201.26]) by mail.rt-rk.com (Postfix) with ESMTPSA id 895841A2130; Mon, 9 Jul 2018 22:52:48 +0200 (CEST) From: Aleksandar Markovic To: qemu-devel@nongnu.org Date: Mon, 9 Jul 2018 22:50:14 +0200 Message-Id: <1531169431-10772-17-git-send-email-aleksandar.markovic@rt-rk.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1531169431-10772-1-git-send-email-aleksandar.markovic@rt-rk.com> References: <1531169431-10772-1-git-send-email-aleksandar.markovic@rt-rk.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [fuzzy] X-Received-From: 89.216.37.149 Subject: [Qemu-devel] [PATCH v2 16/33] target/mips: Implement MT ASE support for nanoMIPS X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: pburton@wavecomp.com, smarkovic@wavecomp.com, f4bug@amsat.org, amarkovic@wavecomp.com, pjovanovic@wavecomp.com, aurelien@aurel32.net Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" From: Stefan Markovic Add emulation of MT ASE instructions for nanoMIPS. Signed-off-by: Aleksandar Markovic Signed-off-by: Stefan Markovic --- target/mips/translate.c | 85 +++++++++++++++++++++++++++++++++++++++++++++++-- 1 file changed, 83 insertions(+), 2 deletions(-) diff --git a/target/mips/translate.c b/target/mips/translate.c index e18e279..c55d809 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -16463,7 +16463,7 @@ static void gen_pool16c_nanomips_insn(DisasContext *ctx) } } -static void gen_pool32a0_nanomips_insn(DisasContext *ctx) +static void gen_pool32a0_nanomips_insn(CPUMIPSState *env, DisasContext *ctx) { int rt = (ctx->opcode >> 21) & 0x1f; int rs = (ctx->opcode >> 16) & 0x1f; @@ -16636,6 +16636,87 @@ static void gen_pool32a0_nanomips_insn(DisasContext *ctx) tcg_temp_free(t0); } break; + case NM_D_E_MT_VPE: + { + uint8_t sc = (ctx->opcode >> 10) & 1; + TCGv t0 = tcg_temp_new(); + + switch (sc) { + case 0: + if (rs == 1) { + /* DMT */ + check_insn(ctx, ASE_MT); + gen_helper_dmt(t0); + gen_store_gpr(t0, rt); + } else if (rs == 0) { + /* DVPE */ + check_insn(ctx, ASE_MT); + gen_helper_dvpe(t0, cpu_env); + gen_store_gpr(t0, rt); + } else { + generate_exception_end(ctx, EXCP_RI); + } + break; + case 1: + if (rs == 1) { + /* EMT */ + check_insn(ctx, ASE_MT); + gen_helper_emt(t0); + gen_store_gpr(t0, rt); + } else if (rs == 0) { + /* EVPE */ + check_insn(ctx, ASE_MT); + gen_helper_evpe(t0, cpu_env); + gen_store_gpr(t0, rt); + } else { + generate_exception_end(ctx, EXCP_RI); + } + break; + } + + tcg_temp_free(t0); + } + break; + case NM_FORK: + check_insn(ctx, ASE_MT); + { + TCGv t0 = tcg_temp_new(); + TCGv t1 = tcg_temp_new(); + + gen_load_gpr(t0, rt); + gen_load_gpr(t1, rs); + gen_helper_fork(t0, t1); + tcg_temp_free(t0); + tcg_temp_free(t1); + } + break; + case NM_MFTR: + case NM_MFHTR: + check_insn(ctx, ASE_MT); + if (rd == 0) { + /* Treat as NOP. */ + return; + } + gen_mftr(env, ctx, rs, rt, (ctx->opcode >> 10) & 1, + (ctx->opcode >> 11) & 0x1f, (ctx->opcode >> 3) & 1); + break; + case NM_MTTR: + case NM_MTHTR: + check_insn(ctx, ASE_MT); + gen_mttr(env, ctx, rs, rt, (ctx->opcode >> 10) & 1, + (ctx->opcode >> 11) & 0x1f, (ctx->opcode >> 3) & 1); + break; + case NM_YIELD: + check_insn(ctx, ASE_MT); + { + TCGv t0 = tcg_temp_new(); + + gen_load_gpr(t0, rs); + gen_helper_yield(t0, cpu_env, t0); + gen_store_gpr(t0, rt); + tcg_temp_free(t0); + } + break; #endif default: generate_exception_end(ctx, EXCP_RI); @@ -17385,7 +17466,7 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *env, DisasContext *ctx) case NM_POOL32A: switch (ctx->opcode & 0x07) { case NM_POOL32A0: - gen_pool32a0_nanomips_insn(ctx); + gen_pool32a0_nanomips_insn(env, ctx); break; case NM_POOL32A7: {