From patchwork Fri May 4 03:57:33 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Liu, Jingqi" X-Patchwork-Id: 907806 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=208.118.235.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=intel.com Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 40bzNc3QMGz9s2k for ; Thu, 3 May 2018 12:19:12 +1000 (AEST) Received: from localhost ([::1]:53479 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fE3pu-000554-6f for incoming@patchwork.ozlabs.org; Wed, 02 May 2018 22:19:10 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:50874) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fE3pG-00053S-7b for qemu-devel@nongnu.org; Wed, 02 May 2018 22:18:31 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fE3pD-0002gF-3c for qemu-devel@nongnu.org; Wed, 02 May 2018 22:18:30 -0400 Received: from mga05.intel.com ([192.55.52.43]:31219) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1fE3pC-0002fc-Q8 for qemu-devel@nongnu.org; Wed, 02 May 2018 22:18:27 -0400 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by fmsmga105.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 02 May 2018 19:18:25 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.49,356,1520924400"; d="scan'208";a="42636696" Received: from dst.sh.intel.com ([10.239.48.156]) by fmsmga002.fm.intel.com with ESMTP; 02 May 2018 19:18:24 -0700 From: Jingqi Liu To: qemu-devel@nongnu.org Date: Fri, 4 May 2018 11:57:33 +0800 Message-Id: <1525406253-54846-1-git-send-email-jingqi.liu@intel.com> X-Mailer: git-send-email 1.8.3.1 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 192.55.52.43 Subject: [Qemu-devel] [PATCH] x86/cpu: Enable CLDEMOTE(Demote Cache Line) cpu feature X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: pbonzini@redhat.com, Jingqi Liu , ehabkost@redhat.com, rth@twiddle.net Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" The CLDEMOTE instruction hints to hardware that the cache line that contains the linear address should be moved("demoted") from the cache(s) closest to the processor core to a level more distant from the processor core. This may accelerate subsequent accesses to the line by other cores in the same coherence domain, especially if the line was written by the core that demotes the line. Intel Snow Ridge has added new cpu feature, CLDEMOTE. The new cpu feature needs to be exposed to guest VM. The bit definition: CPUID.(EAX=7,ECX=0):ECX[bit 25] CLDEMOTE The release document ref below link: https://software.intel.com/sites/default/files/managed/c5/15/\ architecture-instruction-set-extensions-programming-reference.pdf Signed-off-by: Jingqi Liu Reviewed-by: Eduardo Habkost --- target/i386/cpu.c | 2 +- target/i386/cpu.h | 1 + 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index ec1efd3..d5a5abf 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -483,7 +483,7 @@ static FeatureWordInfo feature_word_info[FEATURE_WORDS] = { "avx512bitalg", NULL, "avx512-vpopcntdq", NULL, "la57", NULL, NULL, NULL, NULL, NULL, "rdpid", NULL, - NULL, NULL, NULL, NULL, + NULL, "cldemote", NULL, NULL, NULL, NULL, NULL, NULL, }, .cpuid_eax = 7, diff --git a/target/i386/cpu.h b/target/i386/cpu.h index 0c3f514..3ef90e0 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -678,6 +678,7 @@ typedef uint32_t FeatureWordArray[FEATURE_WORDS]; #define CPUID_7_0_ECX_AVX512_VPOPCNTDQ (1U << 14) /* POPCNT for vectors of DW/QW */ #define CPUID_7_0_ECX_LA57 (1U << 16) #define CPUID_7_0_ECX_RDPID (1U << 22) +#define CPUID_7_0_ECX_CLDEMOTE (1U << 25) /* CLDEMOTE Instruction */ #define CPUID_7_0_EDX_AVX512_4VNNIW (1U << 2) /* AVX512 Neural Network Instructions */ #define CPUID_7_0_EDX_AVX512_4FMAPS (1U << 3) /* AVX512 Multiply Accumulation Single Precision */