From patchwork Fri Apr 20 18:55:17 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Emilio Cota X-Patchwork-Id: 902131 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=2001:4830:134:3::11; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=braap.org Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=braap.org header.i=@braap.org header.b="RzQeNLzr"; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=messagingengine.com header.i=@messagingengine.com header.b="YZx3yyih"; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 40SQGV5LWVz9s1d for ; Sat, 21 Apr 2018 05:02:41 +1000 (AEST) Received: from localhost ([::1]:52857 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1f9bIs-0002mj-Li for incoming@patchwork.ozlabs.org; Fri, 20 Apr 2018 15:02:38 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:60588) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1f9bBu-0005dg-SY for qemu-devel@nongnu.org; Fri, 20 Apr 2018 14:55:31 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1f9bBr-00022H-HF for qemu-devel@nongnu.org; Fri, 20 Apr 2018 14:55:26 -0400 Received: from out3-smtp.messagingengine.com ([66.111.4.27]:46949) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1f9bBr-00021S-6F for qemu-devel@nongnu.org; Fri, 20 Apr 2018 14:55:23 -0400 Received: from compute4.internal (compute4.nyi.internal [10.202.2.44]) by mailout.nyi.internal (Postfix) with ESMTP id A522621D89; Fri, 20 Apr 2018 14:55:22 -0400 (EDT) Received: from mailfrontend2 ([10.202.2.163]) by compute4.internal (MEProxy); Fri, 20 Apr 2018 14:55:22 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=braap.org; h=cc :date:from:in-reply-to:message-id:references:subject:to :x-me-sender:x-me-sender:x-sasl-enc; s=mesmtp; bh=iTPC8e/DVXvt9+ vnF90k7VpLEiCe8pq2MDKrSoUldYI=; b=RzQeNLzrEisMCiB12nkZzvz1GVxtCT J1jpzikkbdb403mRO1mXollD2iqLSnXeg7JsMCDPXQZ3rpu8Mql0PvPLt7T/quWx CcKFXKMUxLG5xUF2+7tVJtoFTgAHJsBqser+VUVNzs/2H8Vq6PEyN14TqSouKVlO vgT+QF3BuqeEw= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d= messagingengine.com; h=cc:date:from:in-reply-to:message-id :references:subject:to:x-me-sender:x-me-sender:x-sasl-enc; s= fm2; bh=iTPC8e/DVXvt9+vnF90k7VpLEiCe8pq2MDKrSoUldYI=; b=YZx3yyih 4sjpfku4kNTCeAN5vDS0KHadS2K4T4PdK7dyKhPET2SyWemJva6d9/6epiWMT7UR s1wRGhTIxCuEfUcqMbLqTfUsDPsqEVpgmpQn5Pk/wx9Dextih11ocW+1WNe7ahdx 0SAopZIW7orrhAZKl14zXzAZy19GAqamv5epXEnl14c2NnbqYvpPZanhJ2Z4gHdu z/SSk1D27kw/SrmcZmtJxVvU9VhWG32BHA2jsvHszaR7qDzp6Sgat7buwnmbzroN 0CcykmQbvbPNGjB1ENeb9kz+1o0EEaB6NiTDUvmY6+iq5YLzXQUhvCmD0uV0mF/f 6bW66NoQ18L4fA== X-ME-Sender: Received: from localhost (flamenco.cs.columbia.edu [128.59.20.216]) by mail.messagingengine.com (Postfix) with ESMTPA id 5D68310256; Fri, 20 Apr 2018 14:55:22 -0400 (EDT) From: "Emilio G. Cota" To: qemu-devel@nongnu.org Date: Fri, 20 Apr 2018 14:55:17 -0400 Message-Id: <1524250517-28032-19-git-send-email-cota@braap.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1524250517-28032-1-git-send-email-cota@braap.org> References: <1524250517-28032-1-git-send-email-cota@braap.org> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 66.111.4.27 Subject: [Qemu-devel] [PATCH 18/18] target/riscv: convert to TranslatorOps X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Bastian Koppelmann , Michael Clark , Richard Henderson , Sagar Karandikar , Palmer Dabbelt Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Reviewed-by: Richard Henderson Cc: Michael Clark Cc: Palmer Dabbelt Cc: Sagar Karandikar Cc: Bastian Koppelmann Signed-off-by: Emilio G. Cota Reviewed-by: Michael Clark --- target/riscv/translate.c | 158 ++++++++++++++++++++++++----------------------- 1 file changed, 80 insertions(+), 78 deletions(-) diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 18ec1a7..fc9c659 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -1836,78 +1836,71 @@ static void decode_opc(CPURISCVState *env, DisasContext *ctx) } } -void gen_intermediate_code(CPUState *cs, TranslationBlock *tb) +static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) { - CPURISCVState *env = cs->env_ptr; - DisasContext ctx; - target_ulong page_start; - int num_insns; - int max_insns; - - ctx.base.pc_first = tb->pc; - ctx.base.pc_next = ctx.base.pc_first; - /* once we have GDB, the rest of the translate.c implementation should be - ready for singlestep */ - ctx.base.singlestep_enabled = cs->singlestep_enabled; - ctx.base.tb = tb; - ctx.base.is_jmp = DISAS_NEXT; - - page_start = ctx.base.pc_first & TARGET_PAGE_MASK; - ctx.pc_succ_insn = ctx.base.pc_first; - ctx.flags = tb->flags; - ctx.mem_idx = tb->flags & TB_FLAGS_MMU_MASK; - ctx.frm = -1; /* unknown rounding mode */ - - num_insns = 0; - max_insns = tb_cflags(ctx.base.tb) & CF_COUNT_MASK; - if (max_insns == 0) { - max_insns = CF_COUNT_MASK; - } - if (max_insns > TCG_MAX_INSNS) { - max_insns = TCG_MAX_INSNS; - } - gen_tb_start(tb); + DisasContext *ctx = container_of(dcbase, DisasContext, base); - while (ctx.base.is_jmp == DISAS_NEXT) { - tcg_gen_insn_start(ctx.base.pc_next); - num_insns++; + ctx->pc_succ_insn = ctx->base.pc_first; + ctx->flags = ctx->base.tb->flags; + ctx->mem_idx = ctx->base.tb->flags & TB_FLAGS_MMU_MASK; + ctx->frm = -1; /* unknown rounding mode */ +} - if (unlikely(cpu_breakpoint_test(cs, ctx.base.pc_next, BP_ANY))) { - tcg_gen_movi_tl(cpu_pc, ctx.base.pc_next); - ctx.base.is_jmp = DISAS_NORETURN; - gen_exception_debug(); - /* The address covered by the breakpoint must be included in - [tb->pc, tb->pc + tb->size) in order to for it to be - properly cleared -- thus we increment the PC here so that - the logic setting tb->size below does the right thing. */ - ctx.base.pc_next += 4; - goto done_generating; - } +static void riscv_tr_tb_start(DisasContextBase *db, CPUState *cpu) +{ +} - if (num_insns == max_insns && (tb_cflags(ctx.base.tb) & CF_LAST_IO)) { - gen_io_start(); - } +static void riscv_tr_insn_start(DisasContextBase *dcbase, CPUState *cpu) +{ + DisasContext *ctx = container_of(dcbase, DisasContext, base); + + tcg_gen_insn_start(ctx->base.pc_next); +} + +static bool riscv_tr_breakpoint_check(DisasContextBase *dcbase, CPUState *cpu, + const CPUBreakpoint *bp) +{ + DisasContext *ctx = container_of(dcbase, DisasContext, base); + + tcg_gen_movi_tl(cpu_pc, ctx->base.pc_next); + ctx->base.is_jmp = DISAS_NORETURN; + gen_exception_debug(); + /* The address covered by the breakpoint must be included in + [tb->pc, tb->pc + tb->size) in order to for it to be + properly cleared -- thus we increment the PC here so that + the logic setting tb->size below does the right thing. */ + ctx->base.pc_next += 4; + return true; +} + + +static void riscv_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu) +{ + DisasContext *ctx = container_of(dcbase, DisasContext, base); + CPURISCVState *env = cpu->env_ptr; + + ctx->opcode = cpu_ldl_code(env, ctx->base.pc_next); + decode_opc(env, ctx); + ctx->base.pc_next = ctx->pc_succ_insn; + + if (ctx->base.is_jmp == DISAS_NEXT) { + target_ulong page_start; - ctx.opcode = cpu_ldl_code(env, ctx.base.pc_next); - decode_opc(env, &ctx); - ctx.base.pc_next = ctx.pc_succ_insn; - - if (ctx.base.is_jmp == DISAS_NEXT && - (cs->singlestep_enabled || - ctx.base.pc_next - page_start >= TARGET_PAGE_SIZE || - tcg_op_buf_full() || - num_insns >= max_insns || - singlestep)) { - ctx.base.is_jmp = DISAS_TOO_MANY; + page_start = ctx->base.pc_first & TARGET_PAGE_MASK; + if (ctx->base.pc_next - page_start >= TARGET_PAGE_SIZE) { + ctx->base.is_jmp = DISAS_TOO_MANY; } } - if (tb_cflags(ctx.base.tb) & CF_LAST_IO) { - gen_io_end(); - } - switch (ctx.base.is_jmp) { +} + +static void riscv_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu) +{ + DisasContext *ctx = container_of(dcbase, DisasContext, base); + + switch (ctx->base.is_jmp) { case DISAS_TOO_MANY: - tcg_gen_movi_tl(cpu_pc, ctx.base.pc_next); - if (cs->singlestep_enabled) { + tcg_gen_movi_tl(cpu_pc, ctx->base.pc_next); + if (ctx->base.singlestep_enabled) { gen_exception_debug(); } else { tcg_gen_exit_tb(0); @@ -1918,20 +1911,29 @@ void gen_intermediate_code(CPUState *cs, TranslationBlock *tb) default: g_assert_not_reached(); } -done_generating: - gen_tb_end(tb, num_insns); - tb->size = ctx.base.pc_next - ctx.base.pc_first; - tb->icount = num_insns; - -#ifdef DEBUG_DISAS - if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM) - && qemu_log_in_addr_range(ctx.base.pc_first)) { - qemu_log("IN: %s\n", lookup_symbol(ctx.base.pc_first)); - log_target_disas(cs, ctx.base.pc_first, - ctx.base.pc_next - ctx.base.pc_first); - qemu_log("\n"); - } -#endif +} + +static void riscv_tr_disas_log(const DisasContextBase *dcbase, CPUState *cpu) +{ + qemu_log("IN: %s\n", lookup_symbol(dcbase->pc_first)); + log_target_disas(cpu, dcbase->pc_first, dcbase->tb->size); +} + +static const TranslatorOps riscv_tr_ops = { + .init_disas_context = riscv_tr_init_disas_context, + .tb_start = riscv_tr_tb_start, + .insn_start = riscv_tr_insn_start, + .breakpoint_check = riscv_tr_breakpoint_check, + .translate_insn = riscv_tr_translate_insn, + .tb_stop = riscv_tr_tb_stop, + .disas_log = riscv_tr_disas_log, +}; + +void gen_intermediate_code(CPUState *cs, TranslationBlock *tb) +{ + DisasContext ctx; + + translator_loop(&riscv_tr_ops, &ctx.base, cs, tb); } void riscv_translate_init(void)