| Message ID | 1519782697-13100-1-git-send-email-wei.guo.simon@gmail.com |
|---|---|
| State | New |
| Headers | show |
| Series | PowerPC: Add TM bits into msr_mask | expand |
On Wed, Feb 28, 2018 at 09:51:37AM +0800, wei.guo.simon@gmail.com wrote: > From: Simon Guo <wei.guo.simon@gmail.com> > > During migration, cpu_post_load() will use msr_mask to determine which > PPC MSR bits will be sync to the target side. Hardware Transaction > Memory(HTM) has been supported since Power8. This patch adds TM/TS bits > into msr_mask for Power8, so that transactional application can be > migrated across qemu. > > Signed-off-by: Simon Guo <wei.guo.simon@gmail.com> Sorry I've taken a while to respond to this. This addresses a real bug, but doesn't get the details quite right. First, the MSR_TM bit is *already* included in the msr_mask for POWER8 (it's a little above the context for this patch), though TS0 and TS1 were not. Second, all MSR bits are sent to the far side, it's just that without them in the MSR mask they'll be dropped instead of re-inserted into KVM. That's the only reason the msr_mask is relevant to KVM (and TCG doesn't support HTM anyway). The commit message needs to make that clearer. > --- > target/ppc/translate_init.c | 3 +++ > 1 file changed, 3 insertions(+) > > diff --git a/target/ppc/translate_init.c b/target/ppc/translate_init.c > index 55c99c9..a438721 100644 > --- a/target/ppc/translate_init.c > +++ b/target/ppc/translate_init.c > @@ -8689,6 +8689,9 @@ POWERPC_FAMILY(POWER8)(ObjectClass *oc, void *data) > (1ull << MSR_DR) | > (1ull << MSR_PMM) | > (1ull << MSR_RI) | > + (1ull << MSR_TM) | > + (1ull << MSR_TS0) | > + (1ull << MSR_TS1) | > (1ull << MSR_LE); > pcc->mmu_model = POWERPC_MMU_2_07; > #if defined(CONFIG_SOFTMMU)
Hi David, On Mon, Mar 05, 2018 at 05:22:33PM +1100, David Gibson wrote: > On Wed, Feb 28, 2018 at 09:51:37AM +0800, wei.guo.simon@gmail.com wrote: > > From: Simon Guo <wei.guo.simon@gmail.com> > > > > During migration, cpu_post_load() will use msr_mask to determine which > > PPC MSR bits will be sync to the target side. Hardware Transaction > > Memory(HTM) has been supported since Power8. This patch adds TM/TS bits > > into msr_mask for Power8, so that transactional application can be > > migrated across qemu. > > > > Signed-off-by: Simon Guo <wei.guo.simon@gmail.com> > > Sorry I've taken a while to respond to this. > > This addresses a real bug, but doesn't get the details quite right. > > First, the MSR_TM bit is *already* included in the msr_mask for POWER8 > (it's a little above the context for this patch), though TS0 and TS1 > were not. > > Second, all MSR bits are sent to the far side, it's just that without > them in the MSR mask they'll be dropped instead of re-inserted into > KVM. That's the only reason the msr_mask is relevant to KVM (and TCG > doesn't support HTM anyway). The commit message needs to make that clearer. > Thanks for the comments. I have sent v2 to correct the above. Regards, - Simon
diff --git a/target/ppc/translate_init.c b/target/ppc/translate_init.c index 55c99c9..a438721 100644 --- a/target/ppc/translate_init.c +++ b/target/ppc/translate_init.c @@ -8689,6 +8689,9 @@ POWERPC_FAMILY(POWER8)(ObjectClass *oc, void *data) (1ull << MSR_DR) | (1ull << MSR_PMM) | (1ull << MSR_RI) | + (1ull << MSR_TM) | + (1ull << MSR_TS0) | + (1ull << MSR_TS1) | (1ull << MSR_LE); pcc->mmu_model = POWERPC_MMU_2_07; #if defined(CONFIG_SOFTMMU)