[v4,01/22] RISC-V Maintainers

Message ID	1517811767-75958-1-git-send-email-mjc@sifive.com
State	New
Headers	show Return-Path: <qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org> From: Michael Clark <mjc@sifive.com> To: qemu-devel@nongnu.org Date: Mon, 5 Feb 2018 19:22:26 +1300 Message-Id: <1517811767-75958-1-git-send-email-mjc@sifive.com> Subject: [Qemu-devel] [PATCH v4 01/22] RISC-V Maintainers Precedence: list Cc: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>, Michael Clark <mjc@sifive.com>, Palmer Dabbelt <palmer@sifive.com>, Sagar Karandikar <sagark@eecs.berkeley.edu>, RISC-V Patches <patches@groups.riscv.org> Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" <qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>
Series	[v4,01/22] RISC-V Maintainers \| expand [v4,01/22] RISC-V Maintainers [v4,02/22] RISC-V ELF Machine Definition [v4,03/22] RISC-V CPU Core Definition [v4,04/22] RISC-V Disassembler [v4,05/22] RISC-V CPU Helpers [v4,06/22] RISC-V FPU Support [v4,07/22] RISC-V GDB Stub [v4,08/22] RISC-V TCG Code Generation [v4,09/22] RISC-V Physical Memory Protection [v4,10/22] RISC-V Linux User Emulation [v4,11/22] RISC-V HTIF Console [v4,12/22] RISC-V HART Array [v4,13/22] SiFive RISC-V CLINT Block [v4,14/22] SiFive RISC-V PLIC Block [v4,15/22] RISC-V Spike Machines [v4,16/22] RISC-V VirtIO Machine [v4,17/22] SiFive RISC-V UART Device [v4,18/22] SiFive RISC-V PRCI Block [v4,19/22] SiFive RISC-V Test Finisher [v4,20/22] SiFive Freedom E300 RISC-V Machine [v4,21/22] SiFive Freedom U500 RISC-V Machine [v4,22/22] RISC-V Build Infrastructure

Message ID

1517811767-75958-1-git-send-email-mjc@sifive.com

State

New

Headers

From: Michael Clark <mjc@sifive.com>
To: qemu-devel@nongnu.org
Date: Mon,  5 Feb 2018 19:22:26 +1300
Message-Id: <1517811767-75958-1-git-send-email-mjc@sifive.com>
Subject: [Qemu-devel] [PATCH v4 01/22] RISC-V Maintainers
Precedence: list
Cc: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>,
	Michael Clark <mjc@sifive.com>, Palmer Dabbelt <palmer@sifive.com>,
	Sagar Karandikar <sagark@eecs.berkeley.edu>,
	RISC-V Patches <patches@groups.riscv.org>
Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org
Sender: "Qemu-devel"
	<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>

Series

[v4,01/22] RISC-V Maintainers | expand

Commit Message

Michael Clark Feb. 5, 2018, 6:22 a.m. UTC

Add Michael Clark, Palmer Dabbelt, Sagar Karandikar and Bastian
Koppelmann as RISC-V Maintainers.

Signed-off-by: Michael Clark <mjc@sifive.com>
---
 MAINTAINERS | 11 +++++++++++
 1 file changed, 11 insertions(+)

diff --git a/MAINTAINERS b/MAINTAINERS
index 0f952d4..d607039 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -210,6 +210,17 @@  F: hw/ppc/
 F: include/hw/ppc/
 F: disas/ppc.c
 
+RISC-V
+M: Michael Clark <mjc@sifive.com>
+M: Palmer Dabbelt <palmer@sifive.com>
+M: Sagar Karandikar <sagark@eecs.berkeley.edu>
+M: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
+S: Maintained
+F: target/riscv/
+F: hw/riscv/
+F: include/hw/riscv/
+F: disas/riscv.c
+
 S390
 M: Richard Henderson <rth@twiddle.net>
 M: Alexander Graf <agraf@suse.de>