From patchwork Wed Jan 10 23:46:37 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michael Clark X-Patchwork-Id: 858654 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=2001:4830:134:3::11; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=sifive.com header.i=@sifive.com header.b="WYK5AeRA"; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3zH5bN3n47z9s8J for ; Thu, 11 Jan 2018 10:59:44 +1100 (AEDT) Received: from localhost ([::1]:50429 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eZQHV-0007OO-VF for incoming@patchwork.ozlabs.org; Wed, 10 Jan 2018 18:59:42 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:45079) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eZQ7R-0006RS-EX for qemu-devel@nongnu.org; Wed, 10 Jan 2018 18:49:20 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1eZQ7O-0000du-G7 for qemu-devel@nongnu.org; Wed, 10 Jan 2018 18:49:17 -0500 Received: from mail-pg0-x242.google.com ([2607:f8b0:400e:c05::242]:37398) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1eZQ7N-0000ck-Mo for qemu-devel@nongnu.org; Wed, 10 Jan 2018 18:49:14 -0500 Received: by mail-pg0-x242.google.com with SMTP id z17so1114234pgc.4 for ; Wed, 10 Jan 2018 15:49:13 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=lBBzFAIA2xh4zyrMWM0R1i0A+u2qLLwVZpPU2flCzqA=; b=WYK5AeRAFhIsdHc8mUKiUVaFxsZF8sCbxoCejTbIC7k+EyLKwgtkLrrnkqtRml9Ae7 4m8LnFAiuNmG5IeaLD1TLBPGaOHV5DTI3/Jdl06PPeGrgUuBMLvYbjVMLrLkNKl+AE0X QKuI8uh7yv7VGPeDfBBPWAl8L1LfpZbYYKelTe1c2VebR5YdX+B8SbfQYt8RcZhtAQHz Qi0yQubhjy9lYeXUAR3Ih4wLDbyw4Yic49jYP/IjVcOBh9py3FogGwf3ZgWPahkI2SvI HbgZp0IJu+HWGrRjxcLNwDWpRxAC8XWRu3GaetQyTDFxv7ffAwtlLaAjphn9gXLTXXXT f01A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=lBBzFAIA2xh4zyrMWM0R1i0A+u2qLLwVZpPU2flCzqA=; b=d+14+oZm+w+hgwmF5HL7OV3H386F8C0z0Syn46LErllVq4iwNLhmMEIuIzk6Mw274+ MS0g7f231RBEUQi55/9SsBMFmSRNMBXw4y0NscagEHBnoBryfvUcDnSlTHXsYmMRKRCr dZz4fk9JKPZbYqKymJLHyUxVy+t1c45ZjSXxBVFMWbCqpUGSrZE8p6zy7XQIcGlmF1jI hSON4DbQ83B4jtEOhZ99rdLHrXgRNeVPRb2hAQ6vBmo7iGkvsEV/lawKYU5paZB6E1Qf o9E8YhQJRedVLDe7HPD04oXXZSfPPXVC9b0luJ+eRmTLH2yUozZ6nIorIG1Jy+hEhLzH bqCg== X-Gm-Message-State: AKGB3mKOe3S68WuTGLfcm/LJh+3ShBa0IgXtb1RQG+ZVYJAMxf3PKfUV Z7VHiW+6TXIasyR+PXUpwh3F5H+SrQU= X-Google-Smtp-Source: ACJfBouF/Mm97Y02T3c1/XQiGN5iKSBQ3o8RohXuo4PhL4q4z8sHPvNRSf0hrVJa0OXkYw9bJFxMdg== X-Received: by 10.98.210.5 with SMTP id c5mr11443620pfg.238.1515628152550; Wed, 10 Jan 2018 15:49:12 -0800 (PST) Received: from monty.com ([12.206.222.5]) by smtp.gmail.com with ESMTPSA id g74sm9931676pfd.166.2018.01.10.15.49.11 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 10 Jan 2018 15:49:11 -0800 (PST) From: Michael Clark To: qemu-devel@nongnu.org Date: Wed, 10 Jan 2018 15:46:37 -0800 Message-Id: <1515628000-93285-19-git-send-email-mjc@sifive.com> X-Mailer: git-send-email 2.7.0 In-Reply-To: <1515628000-93285-1-git-send-email-mjc@sifive.com> References: <1515628000-93285-1-git-send-email-mjc@sifive.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::242 Subject: [Qemu-devel] [PATCH v2 18/21] SiFive RISC-V PRCI Block X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Bastian Koppelmann , RISC-V Patches , Michael Clark , Palmer Dabbelt , Sagar Karandikar Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Simple model of the PRCI (Power, Reset, Clock, Interrupt) to emulate register reads made by the SDK BSP. Signed-off-by: Michael Clark --- hw/riscv/sifive_prci.c | 107 +++++++++++++++++++++++++++++++++++++++++ include/hw/riscv/sifive_prci.h | 43 +++++++++++++++++ 2 files changed, 150 insertions(+) create mode 100644 hw/riscv/sifive_prci.c create mode 100644 include/hw/riscv/sifive_prci.h diff --git a/hw/riscv/sifive_prci.c b/hw/riscv/sifive_prci.c new file mode 100644 index 0000000..5c27696 --- /dev/null +++ b/hw/riscv/sifive_prci.c @@ -0,0 +1,107 @@ +/* + * QEMU SiFive PRCI (Power, Reset, Clock, Interrupt) + * + * Copyright (c) 2017 SiFive, Inc. + * + * Simple model of the PRCI to emulate register reads made by the SDK BSP + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#include "qemu/osdep.h" +#include "hw/sysbus.h" +#include "target/riscv/cpu.h" +#include "hw/riscv/sifive_prci.h" + +/* currently implements enough to mock freedom-e-sdk BSP clock programming */ + +static uint64_t sifive_prci_read(void *opaque, hwaddr addr, unsigned int size) +{ + if (addr == 0 /* PRCI_HFROSCCFG */) { + return 1 << 31; /* ROSC_RDY */ + } + if (addr == 8 /* PRCI_PLLCFG */) { + return 1 << 31; /* PLL_LOCK */ + } + hw_error("%s: read: addr=0x%x\n", __func__, (int)addr); + return 0; +} + +static void sifive_prci_write(void *opaque, hwaddr addr, + uint64_t val64, unsigned int size) +{ + /* discard writes */ +} + +static const MemoryRegionOps sifive_prci_ops = { + .read = sifive_prci_read, + .write = sifive_prci_write, + .endianness = DEVICE_NATIVE_ENDIAN, + .valid = { + .min_access_size = 4, + .max_access_size = 4 + } +}; + +static Property sifive_prci_properties[] = { + DEFINE_PROP_END_OF_LIST(), +}; + +static void sifive_prci_init(Object *obj) +{ + SiFivePRCIState *s = SIFIVE_PRCI(obj); + + memory_region_init_io(&s->mmio, obj, &sifive_prci_ops, s, + TYPE_SIFIVE_PRCI, 0x8000); + sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->mmio); +} + +static void sifive_prci_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + + dc->props = sifive_prci_properties; +} + +static const TypeInfo sifive_prci_info = { + .name = TYPE_SIFIVE_PRCI, + .parent = TYPE_SYS_BUS_DEVICE, + .instance_size = sizeof(SiFivePRCIState), + .instance_init = sifive_prci_init, + .class_init = sifive_prci_class_init, +}; + +static void sifive_prci_register_types(void) +{ + type_register_static(&sifive_prci_info); +} + +type_init(sifive_prci_register_types) + + +/* + * Create PRCI device. + */ +DeviceState *sifive_prci_create(hwaddr addr) +{ + DeviceState *dev = qdev_create(NULL, TYPE_SIFIVE_PRCI); + qdev_init_nofail(dev); + sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, addr); + return dev; +} diff --git a/include/hw/riscv/sifive_prci.h b/include/hw/riscv/sifive_prci.h new file mode 100644 index 0000000..0e032e5 --- /dev/null +++ b/include/hw/riscv/sifive_prci.h @@ -0,0 +1,43 @@ +/* + * QEMU SiFive PRCI (Power, Reset, Clock, Interrupt) interface + * + * Copyright (c) 2017 SiFive, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#ifndef HW_SIFIVE_PRCI_H +#define HW_SIFIVE_PRCI_H + +#define TYPE_SIFIVE_PRCI "riscv.sifive.prci" + +#define SIFIVE_PRCI(obj) \ + OBJECT_CHECK(SiFivePRCIState, (obj), TYPE_SIFIVE_PRCI) + +typedef struct SiFivePRCIState { + /*< private >*/ + SysBusDevice parent_obj; + + /*< public >*/ + MemoryRegion mmio; +} SiFivePRCIState; + +DeviceState *sifive_prci_create(hwaddr addr); + +#endif