[v1,02/21] RISC-V ELF Machine Definition

Message ID	1514940265-18093-3-git-send-email-mjc@sifive.com
State	New
Headers	show Return-Path: <qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org> From: Michael Clark <mjc@sifive.com> To: qemu-devel@nongnu.org Date: Wed, 3 Jan 2018 13:44:06 +1300 Message-Id: <1514940265-18093-3-git-send-email-mjc@sifive.com> In-Reply-To: <1514940265-18093-1-git-send-email-mjc@sifive.com> References: <1514940265-18093-1-git-send-email-mjc@sifive.com> Subject: [Qemu-devel] [PATCH v1 02/21] RISC-V ELF Machine Definition Precedence: list Cc: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>, Michael Clark <mjc@sifive.com>, Sagar Karandikar <sagark@eecs.berkeley.edu> Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" <qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>
Series	RISC-V QEMU Port Submission v1 \| expand [v1,00/21] RISC-V QEMU Port Submission v1 [v1,01/21] RISC-V Maintainers [v1,02/21] RISC-V ELF Machine Definition [v1,03/21] RISC-V CPU Core Definition [v1,04/21] RISC-V Disassembler [v1,05/21] RISC-V CPU Helpers [v1,06/21] RISC-V FPU Support [v1,07/21] RISC-V GDB Stub [v1,08/21] RISC-V TCG Code Generation [v1,09/21] RISC-V Physical Memory Protection [v1,10/21] RISC-V Linux User Emulation [v1,11/21] RISC-V HTIF Console [v1,12/21] RISC-V HART Array [v1,13/21] SiFive RISC-V CLINT Block [v1,14/21] SiFive RISC-V PLIC Block [v1,15/21] RISC-V Spike Machines [v1,16/21] RISC-V VirtIO Machine [v1,17/21] SiFive RISC-V UART Device [v1,18/21] SiFive RISC-V PRCI Block [v1,19/21] SiFive Freedom E300 RISC-V Machine [v1,20/21] SiFive Freedom U500 RISC-V Machine [v1,21/21] RISC-V Build Infrastructure

Message ID

1514940265-18093-3-git-send-email-mjc@sifive.com

State

New

Headers

From: Michael Clark <mjc@sifive.com>
To: qemu-devel@nongnu.org
Date: Wed,  3 Jan 2018 13:44:06 +1300
Message-Id: <1514940265-18093-3-git-send-email-mjc@sifive.com>
In-Reply-To: <1514940265-18093-1-git-send-email-mjc@sifive.com>
References: <1514940265-18093-1-git-send-email-mjc@sifive.com>
Subject: [Qemu-devel] [PATCH v1 02/21] RISC-V ELF Machine Definition
Precedence: list
Cc: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>,
	Michael Clark <mjc@sifive.com>,
	Sagar Karandikar <sagark@eecs.berkeley.edu>
Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org
Sender: "Qemu-devel"
	<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>

Series

RISC-V QEMU Port Submission v1 | expand

Comments

Richard Henderson Jan. 3, 2018, 5:30 a.m. UTC | #1

On 01/02/2018 04:44 PM, Michael Clark wrote:
> Define RISC-V ELF machine EM_RISCV 243
> 
> Signed-off-by: Michael Clark <mjc@sifive.com>
> ---
>  include/elf.h | 2 ++
>  1 file changed, 2 insertions(+)

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>


r~

Alistair Francis Jan. 9, 2018, 9:33 p.m. UTC | #2

On Tue, Jan 2, 2018 at 4:44 PM, Michael Clark <mjc@sifive.com> wrote:
> Define RISC-V ELF machine EM_RISCV 243
>
> Signed-off-by: Michael Clark <mjc@sifive.com>

Reviewed-by: Alistair Francis <alistair.francis@xilinx.com>

Alistair

> ---
>  include/elf.h | 2 ++
>  1 file changed, 2 insertions(+)
>
> diff --git a/include/elf.h b/include/elf.h
> index e8a515c..8e457fc 100644
> --- a/include/elf.h
> +++ b/include/elf.h
> @@ -112,6 +112,8 @@ typedef int64_t  Elf64_Sxword;
>
>  #define EM_UNICORE32    110     /* UniCore32 */
>
> +#define EM_RISCV        243     /* RISC-V */
> +
>  /*
>   * This is an interim value that we will use until the committee comes
>   * up with a final number.
> --
> 2.7.0
>
>

diff --git a/include/elf.h b/include/elf.h
index e8a515c..8e457fc 100644
--- a/include/elf.h
+++ b/include/elf.h
@@ -112,6 +112,8 @@  typedef int64_t  Elf64_Sxword;
 
 #define EM_UNICORE32    110     /* UniCore32 */
 
+#define EM_RISCV        243     /* RISC-V */
+
 /*
  * This is an interim value that we will use until the committee comes
  * up with a final number.

[v1,02/21] RISC-V ELF Machine Definition

Commit Message

Comments

Patch