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[PULL,14/26] PCI: PCIe access should always be little endian

Message ID 1508036858-13479-15-git-send-email-mst@redhat.com
State New
Headers show
Series [PULL,01/26] xio3130_downstream: Report error if pcie_chassis_add_slot() failed | expand

Commit Message

Michael S. Tsirkin Oct. 15, 2017, 3:23 a.m. UTC 
From: Matt Redfearn <matt.redfearn@imgtec.com>

PCIe busses are always little endian, so set the endianness of the
memory region to little endian rather than native such that operations
work as expected on big endian targets.

Signed-off-by: Matt Redfearn <matt.redfearn@imgtec.com>
Reviewed-by: Marcel Apfelbaum <marcel@redhat.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
---
 hw/pci/pcie_host.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)
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Patch

diff --git a/hw/pci/pcie_host.c b/hw/pci/pcie_host.c
index dcebf57..553db56 100644
--- a/hw/pci/pcie_host.c
+++ b/hw/pci/pcie_host.c
@@ -81,7 +81,7 @@  static uint64_t pcie_mmcfg_data_read(void *opaque,
 static const MemoryRegionOps pcie_mmcfg_ops = {
     .read = pcie_mmcfg_data_read,
     .write = pcie_mmcfg_data_write,
-    .endianness = DEVICE_NATIVE_ENDIAN,
+    .endianness = DEVICE_LITTLE_ENDIAN,
 };
 
 static void pcie_host_init(Object *obj)