From patchwork Thu Aug 10 12:21:38 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: KONRAD Frederic X-Patchwork-Id: 800188 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=2001:4830:134:3::11; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3xSnNG0GHnz9sRg for ; Thu, 10 Aug 2017 22:23:09 +1000 (AEST) Received: from localhost ([::1]:52862 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dfmUV-000882-Rz for incoming@patchwork.ozlabs.org; Thu, 10 Aug 2017 08:23:07 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:48314) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dfmTx-00080N-Cg for qemu-devel@nongnu.org; Thu, 10 Aug 2017 08:22:34 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dfmTt-0004wL-Vg for qemu-devel@nongnu.org; Thu, 10 Aug 2017 08:22:33 -0400 Received: from mel.act-europe.fr ([194.98.77.210]:42697 helo=smtp.eu.adacore.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1dfmTt-0004vq-Mq for qemu-devel@nongnu.org; Thu, 10 Aug 2017 08:22:29 -0400 Received: from localhost (localhost [127.0.0.1]) by filtered-smtp.eu.adacore.com (Postfix) with ESMTP id 7567A8139D; Thu, 10 Aug 2017 14:22:28 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at eu.adacore.com Received: from smtp.eu.adacore.com ([127.0.0.1]) by localhost (smtp.eu.adacore.com [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id oUMarCc-rxMR; Thu, 10 Aug 2017 14:22:28 +0200 (CEST) Received: from openvpn-rw-12.act-europe.fr (unknown [IPv6:2a01:e35:87f0:3180:2b18:7e65:c33:7f62]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.eu.adacore.com (Postfix) with ESMTPSA id 8121F8139B; Thu, 10 Aug 2017 14:22:27 +0200 (CEST) From: KONRAD Frederic To: peter.maydell@linaro.org Date: Thu, 10 Aug 2017 14:21:38 +0200 Message-Id: <1502367698-4539-1-git-send-email-frederic.konrad@adacore.com> X-Mailer: git-send-email 1.8.3.1 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [fuzzy] X-Received-From: 194.98.77.210 Subject: [Qemu-devel] [PATCH for-2.10] xlnx-qspi: add a property for mmio-execution X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: quintela@redhat.com, qemu-devel@nongnu.org, dgilbert@redhat.com, frederic.konrad@adacore.com, edgar.iglesias@gmail.com, alistair.francis@xilinx.com Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" This adds mmio-exec property to workaround the migration bug. When enabled the migration is blocked and will return an error. Signed-off-by: KONRAD Frederic --- hw/ssi/xilinx_spips.c | 41 +++++++++++++++++++++++++++++++++-------- 1 file changed, 33 insertions(+), 8 deletions(-) diff --git a/hw/ssi/xilinx_spips.c b/hw/ssi/xilinx_spips.c index e833028..f763bc3 100644 --- a/hw/ssi/xilinx_spips.c +++ b/hw/ssi/xilinx_spips.c @@ -31,6 +31,8 @@ #include "hw/ssi/ssi.h" #include "qemu/bitops.h" #include "hw/ssi/xilinx_spips.h" +#include "qapi/error.h" +#include "migration/blocker.h" #ifndef XILINX_SPIPS_ERR_DEBUG #define XILINX_SPIPS_ERR_DEBUG 0 @@ -139,6 +141,8 @@ typedef struct { uint8_t lqspi_buf[LQSPI_CACHE_SIZE]; hwaddr lqspi_cached_addr; + Error *migration_blocker; + bool mmio_execution_enabled; } XilinxQSPIPS; typedef struct XilinxSPIPSClass { @@ -500,12 +504,13 @@ static void xilinx_qspips_invalidate_mmio_ptr(XilinxQSPIPS *q) { XilinxSPIPS *s = &q->parent_obj; - if (q->lqspi_cached_addr != ~0ULL) { + if ((q->mmio_execution_enabled) && (q->lqspi_cached_addr != ~0ULL)) { /* Invalidate the current mapped mmio */ memory_region_invalidate_mmio_ptr(&s->mmlqspi, q->lqspi_cached_addr, LQSPI_CACHE_SIZE); - q->lqspi_cached_addr = ~0ULL; } + + q->lqspi_cached_addr = ~0ULL; } static void xilinx_qspips_write(void *opaque, hwaddr addr, @@ -601,12 +606,17 @@ static void *lqspi_request_mmio_ptr(void *opaque, hwaddr addr, unsigned *size, unsigned *offset) { XilinxQSPIPS *q = opaque; - hwaddr offset_within_the_region = addr & ~(LQSPI_CACHE_SIZE - 1); - - lqspi_load_cache(opaque, offset_within_the_region); - *size = LQSPI_CACHE_SIZE; - *offset = offset_within_the_region; - return q->lqspi_buf; + hwaddr offset_within_the_region; + + if (q->mmio_execution_enabled) { + offset_within_the_region = addr & ~(LQSPI_CACHE_SIZE - 1); + lqspi_load_cache(opaque, offset_within_the_region); + *size = LQSPI_CACHE_SIZE; + *offset = offset_within_the_region; + return q->lqspi_buf; + } else { + return NULL; + } } static uint64_t @@ -693,6 +703,15 @@ static void xilinx_qspips_realize(DeviceState *dev, Error **errp) sysbus_init_mmio(sbd, &s->mmlqspi); q->lqspi_cached_addr = ~0ULL; + + /* mmio_execution breaks migration better aborting than having strange + * bugs. + */ + if (q->mmio_execution_enabled) { + error_setg(&q->migration_blocker, + "enabling mmio_execution breaks migration"); + migrate_add_blocker(q->migration_blocker, &error_fatal); + } } static int xilinx_spips_post_load(void *opaque, int version_id) @@ -716,6 +735,11 @@ static const VMStateDescription vmstate_xilinx_spips = { } }; +static Property xilinx_qspips_properties[] = { + DEFINE_PROP_BOOL("mmio-exec", XilinxQSPIPS, mmio_execution_enabled, false), + DEFINE_PROP_END_OF_LIST(), +}; + static Property xilinx_spips_properties[] = { DEFINE_PROP_UINT8("num-busses", XilinxSPIPS, num_busses, 1), DEFINE_PROP_UINT8("num-ss-bits", XilinxSPIPS, num_cs, 4), @@ -729,6 +753,7 @@ static void xilinx_qspips_class_init(ObjectClass *klass, void * data) XilinxSPIPSClass *xsc = XILINX_SPIPS_CLASS(klass); dc->realize = xilinx_qspips_realize; + dc->props = xilinx_qspips_properties; xsc->reg_ops = &qspips_ops; xsc->rx_fifo_size = RXFF_A_Q; xsc->tx_fifo_size = TXFF_A_Q;