From patchwork Sat Aug 5 20:29:53 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Aleksandr Bezzubikov X-Patchwork-Id: 798301 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=2001:4830:134:3::11; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="aMxG6YsX"; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3xPwTx0zBJz9sNc for ; Sun, 6 Aug 2017 06:33:09 +1000 (AEST) Received: from localhost ([::1]:58650 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1de5kw-0001ZV-Vn for incoming@patchwork.ozlabs.org; Sat, 05 Aug 2017 16:33:07 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:58197) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1de5i5-0007wW-66 for qemu-devel@nongnu.org; Sat, 05 Aug 2017 16:30:11 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1de5i4-0006Is-4M for qemu-devel@nongnu.org; Sat, 05 Aug 2017 16:30:09 -0400 Received: from mail-lf0-x243.google.com ([2a00:1450:4010:c07::243]:38534) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1de5i3-0006GD-Th for qemu-devel@nongnu.org; Sat, 05 Aug 2017 16:30:08 -0400 Received: by mail-lf0-x243.google.com with SMTP id y15so3063292lfd.5 for ; Sat, 05 Aug 2017 13:30:07 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=4mMVWnBPq5mOMACHoyRiBI8DfjN/qdoD551A0y8uexo=; b=aMxG6YsXpn6ioOFKsBiOu2W2rrJiAnhKMMfklnrXudDintRlfubngRxMTK5WCK78Re hYPPqAxGkmeUyWtXspyNWUw4dIwePYYjYO/w8MSvD+wRFbPpY20j47vcj+a/y6v300rw fBzdxrtRxyqUnZrUA0v9QDM9qM3PgWqXbgS5qADplryMgajAJ5zmxawznc+akJJp7nyN 4SqWlI1DiXLqXqVUXhEa3OF/GxLrmLB5nNVRX5h+d+igd5EYq/76jPHlj7c/0ydTrsm7 StnhLbDkHIuj6x4tkWlMpz1gJWw1PKXSBe5T6E1BJJSMUvlLuJUPTrNX0EhKYBqaoQt3 mOUQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=4mMVWnBPq5mOMACHoyRiBI8DfjN/qdoD551A0y8uexo=; b=PfQGVUGem2OMTY3o0ySR7YFVDvDeFbCXbCBP0b7ER9wLcxgXRDCekIz3V1RDE7h69I +YmsbIiPIE7OrtFy5IRk6QHA2FuEVZYm9LVQ0EqkhjuFe7C3rbu+Xoik1u4+/wUnTyFs ycUj0TvksIG8W7AiKN5W8MsvgQq02apaZOX8DDp1XHoZA+Y39p+3At/+dz9m46pDq79F IvyaBaJvmpK4sTLMvJmU3nRhi3bALrIyjp8QwW0RZNtD/L378ly2FIFzYjh+Tj/EtQ2x qv++rYT2qcqYb7IotzEUvTnSZd7u8Fb0inH7KUfmU9TD0CC9DGCufqj1O06KbzPy750N Hi/A== X-Gm-Message-State: AHYfb5hKZt8YSbGeICoXhfLotBajCsFSBHUURe4vtbPZoL8OYrHx9Xsq ySXdrD12jtSTMw== X-Received: by 10.46.14.9 with SMTP id 9mr2224984ljo.26.1501965006734; Sat, 05 Aug 2017 13:30:06 -0700 (PDT) Received: from localhost.localdomain (broadband-109-173-19-108.moscow.rt.ru. [109.173.19.108]) by smtp.gmail.com with ESMTPSA id 79sm1952439ljf.8.2017.08.05.13.30.05 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Sat, 05 Aug 2017 13:30:05 -0700 (PDT) From: Aleksandr Bezzubikov To: seabios@seabios.org Date: Sat, 5 Aug 2017 23:29:53 +0300 Message-Id: <1501964994-5257-3-git-send-email-zuban32s@gmail.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1501964994-5257-1-git-send-email-zuban32s@gmail.com> References: <1501964994-5257-1-git-send-email-zuban32s@gmail.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4010:c07::243 Subject: [Qemu-devel] [PATCH v4 2/3] pci: add QEMU-specific PCI capability structure X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: mst@redhat.com, qemu-devel@nongnu.org, Aleksandr Bezzubikov , kevin@koconnor.net, kraxel@redhat.com, marcel@redhat.com, lersek@redhat.com Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" On PCI init PCI bridge devices may need some extra info about bus number to reserve, IO, memory and prefetchable memory limits. QEMU can provide this with special vendor-specific PCI capability. This capability is intended to be used only for Red Hat PCI bridges, i.e. QEMU cooperation. Signed-off-by: Aleksandr Bezzubikov --- src/fw/dev-pci.h | 50 ++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 50 insertions(+) create mode 100644 src/fw/dev-pci.h diff --git a/src/fw/dev-pci.h b/src/fw/dev-pci.h new file mode 100644 index 0000000..2c8ddb0 --- /dev/null +++ b/src/fw/dev-pci.h @@ -0,0 +1,50 @@ +#ifndef _PCI_CAP_H +#define _PCI_CAP_H + +#include "types.h" + +/* + +QEMU-specific vendor(Red Hat)-specific capability. +It's intended to provide some hints for firmware to init PCI devices. + +Its structure is shown below: + +Header: + +u8 id; Standard PCI Capability Header field +u8 next; Standard PCI Capability Header field +u8 len; Standard PCI Capability Header field +u8 type; Red Hat vendor-specific capability type: + now only REDHAT_CAP_TYP_QEMU=1 exists +Data: + +u32 bus_res; minimum bus number to reserve; + this is necessary for PCI Express Root Ports + to support PCIE-to-PCI bridge hotplug +u64 io; IO space to reserve +u64 mem; non-prefetchable memory space to reserve +u64 prefetchable_mem; prefetchable memory space to reserve + +If any field value in Data section is -1, +it means that such kind of reservation +is not needed and must be ignored. + +*/ + +/* Offset of vendor-specific capability type field */ +#define PCI_CAP_REDHAT_TYPE 3 + +/* List of valid Red Hat vendor-specific capability types */ +#define REDHAT_CAP_TYPE_QEMU 1 + + +/* Offsets of QEMU capability fields */ +#define QEMU_PCI_CAP_BUS_RES 4 +#define QEMU_PCI_CAP_LIMITS_OFFSET 8 +#define QEMU_PCI_CAP_IO 8 +#define QEMU_PCI_CAP_MEM 16 +#define QEMU_PCI_CAP_PREF_MEM 24 +#define QEMU_PCI_CAP_SIZE 32 + +#endif /* _PCI_CAP_H */