From patchwork Wed Jun 28 13:21:12 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Llu=C3=ADs_Vilanova?= X-Patchwork-Id: 781692 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3wyNk43P5hz9s4q for ; Wed, 28 Jun 2017 23:22:04 +1000 (AEST) Received: from localhost ([::1]:33376 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dQCuw-0003ja-3Z for incoming@patchwork.ozlabs.org; Wed, 28 Jun 2017 09:22:02 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:56372) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dQCuR-0003ir-GO for qemu-devel@nongnu.org; Wed, 28 Jun 2017 09:21:33 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dQCuM-0005TG-JM for qemu-devel@nongnu.org; Wed, 28 Jun 2017 09:21:31 -0400 Received: from roura.ac.upc.es ([147.83.33.10]:60293) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dQCuM-0005So-6V; Wed, 28 Jun 2017 09:21:26 -0400 Received: from correu-2.ac.upc.es (correu-2.ac.upc.es [147.83.30.92]) by roura.ac.upc.es (8.13.8/8.13.8) with ESMTP id v5SDLJmS027342; Wed, 28 Jun 2017 15:21:19 +0200 Received: from localhost (unknown [132.68.50.243]) by correu-2.ac.upc.es (Postfix) with ESMTPSA id C3B511E0; Wed, 28 Jun 2017 15:21:13 +0200 (CEST) From: =?utf-8?b?TGx1w61z?= Vilanova To: qemu-devel@nongnu.org Date: Wed, 28 Jun 2017 16:21:12 +0300 Message-Id: <149865607253.17063.18194249796068858104.stgit@frigg.lan> X-Mailer: git-send-email 2.11.0 In-Reply-To: <149865219962.17063.10630533069463266646.stgit@frigg.lan> References: <149865219962.17063.10630533069463266646.stgit@frigg.lan> User-Agent: StGit/0.17.1-dirty MIME-Version: 1.0 X-MIME-Autoconverted: from 8bit to quoted-printable by roura.ac.upc.es id v5SDLJmS027342 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.6.x [fuzzy] X-Received-From: 147.83.33.10 Subject: [Qemu-devel] [PATCH v11 16/29] target/arm: [tcg, a64] Port to init_disas_context X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , Peter Crosthwaite , "Emilio G. Cota" , "open list:ARM" , Paolo Bonzini , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Richard Henderson Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Incrementally paves the way towards using the generic instruction translation loop. Signed-off-by: Lluís Vilanova Reviewed-by: Richard Henderson --- target/arm/translate-a64.c | 36 ++++++++++++++++++++++-------------- 1 file changed, 22 insertions(+), 14 deletions(-) diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 4270ac3847..88624a726d 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -11190,21 +11190,12 @@ static void disas_a64_insn(CPUARMState *env, DisasContext *s) free_tmp_a64(s); } -void gen_intermediate_code_a64(DisasContextBase *dcbase, CPUState *cs, - TranslationBlock *tb) +static void aarch64_trblock_init_disas_context(DisasContextBase *dcbase, + CPUState *cpu) { - CPUARMState *env = cs->env_ptr; - ARMCPU *cpu = arm_env_get_cpu(env); DisasContext *dc = container_of(dcbase, DisasContext, base); - target_ulong next_page_start; - int max_insns; - - dc->base.tb = tb; - dc->base.pc_first = dc->base.tb->pc; - dc->base.pc_next = dc->base.pc_first; - dc->base.is_jmp = DISAS_NEXT; - dc->base.num_insns = 0; - dc->base.singlestep_enabled = cs->singlestep_enabled; + CPUARMState *env = cpu->env_ptr; + ARMCPU *arm_cpu = arm_env_get_cpu(env); dc->pc = dc->base.pc_first; dc->condjmp = 0; @@ -11230,7 +11221,7 @@ void gen_intermediate_code_a64(DisasContextBase *dcbase, CPUState *cs, dc->fp_excp_el = ARM_TBFLAG_FPEXC_EL(dc->base.tb->flags); dc->vec_len = 0; dc->vec_stride = 0; - dc->cp_regs = cpu->cp_regs; + dc->cp_regs = arm_cpu->cp_regs; dc->features = env->features; /* Single step state. The code-generation logic here is: @@ -11254,6 +11245,23 @@ void gen_intermediate_code_a64(DisasContextBase *dcbase, CPUState *cs, dc->ss_same_el = (arm_debug_target_el(env) == dc->current_el); init_tmp_a64_array(dc); +} + +void gen_intermediate_code_a64(DisasContextBase *dcbase, CPUState *cs, + TranslationBlock *tb) +{ + CPUARMState *env = cs->env_ptr; + DisasContext *dc = container_of(dcbase, DisasContext, base); + target_ulong next_page_start; + int max_insns; + + dc->base.tb = tb; + dc->base.pc_first = dc->base.tb->pc; + dc->base.pc_next = dc->base.pc_first; + dc->base.is_jmp = DISAS_NEXT; + dc->base.num_insns = 0; + dc->base.singlestep_enabled = cs->singlestep_enabled; + aarch64_trblock_init_disas_context(&dc->base, cs); next_page_start = (dc->base.pc_first & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE; max_insns = dc->base.tb->cflags & CF_COUNT_MASK;