From patchwork Thu Jun 22 17:48:26 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Llu=C3=ADs_Vilanova?= X-Patchwork-Id: 779655 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3wtpz36NX3z9t1G for ; Fri, 23 Jun 2017 03:50:55 +1000 (AEST) Received: from localhost ([::1]:60296 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dO6Fp-0004b1-EY for incoming@patchwork.ozlabs.org; Thu, 22 Jun 2017 13:50:53 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:40393) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dO6Df-0002az-B2 for qemu-devel@nongnu.org; Thu, 22 Jun 2017 13:48:40 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dO6Db-0001Sz-Ef for qemu-devel@nongnu.org; Thu, 22 Jun 2017 13:48:39 -0400 Received: from roura.ac.upc.edu ([147.83.33.10]:44899 helo=roura.ac.upc.es) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dO6Db-0001SK-1t for qemu-devel@nongnu.org; Thu, 22 Jun 2017 13:48:35 -0400 Received: from correu-2.ac.upc.es (correu-2.ac.upc.es [147.83.30.92]) by roura.ac.upc.es (8.13.8/8.13.8) with ESMTP id v5MHmXUd009967; Thu, 22 Jun 2017 19:48:33 +0200 Received: from localhost (unknown [31.210.182.235]) by correu-2.ac.upc.es (Postfix) with ESMTPSA id EB4ED880; Thu, 22 Jun 2017 19:48:27 +0200 (CEST) From: =?utf-8?b?TGx1w61z?= Vilanova To: qemu-devel@nongnu.org Date: Thu, 22 Jun 2017 20:48:26 +0300 Message-Id: <149815370652.1830.2785403848458418562.stgit@frigg.lan> X-Mailer: git-send-email 2.11.0 In-Reply-To: <149815338558.1830.8107719559183631163.stgit@frigg.lan> References: <149815338558.1830.8107719559183631163.stgit@frigg.lan> User-Agent: StGit/0.17.1-dirty MIME-Version: 1.0 X-MIME-Autoconverted: from 8bit to quoted-printable by roura.ac.upc.es id v5MHmXUd009967 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.6.x [fuzzy] X-Received-From: 147.83.33.10 Subject: [Qemu-devel] [PATCH v7 10/26] target: [tcg, i386] Refactor breakpoint_check X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Paolo Bonzini , Peter Crosthwaite , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Eduardo Habkost , Richard Henderson Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Incrementally paves the way towards using the generic instruction translation loop. Signed-off-by: Lluís Vilanova --- target/i386/translate.c | 48 +++++++++++++++++++++++++++++++++++------------ 1 file changed, 36 insertions(+), 12 deletions(-) diff --git a/target/i386/translate.c b/target/i386/translate.c index 3c7ef4af67..04d65b8416 100644 --- a/target/i386/translate.c +++ b/target/i386/translate.c @@ -18,6 +18,7 @@ */ #include "qemu/osdep.h" +#include "qemu/error-report.h" #include "qemu/host-utils.h" #include "cpu.h" #include "disas/disas.h" @@ -8474,12 +8475,32 @@ static void i386_trblock_insn_start(DisasContextBase *db, CPUState *cpu) tcg_gen_insn_start(db->pc_next, dc->cc_op); } +static BreakpointCheckType i386_trblock_breakpoint_check( + DisasContextBase *db, CPUState *cpu, const CPUBreakpoint *bp) +{ + DisasContext *dc = container_of(db, DisasContext, base); + /* If RF is set, suppress an internally generated breakpoint. */ + int flags = db->tb->flags & HF_RF_MASK ? BP_GDB : BP_ANY; + if (bp->flags & flags) { + gen_debug(dc, db->pc_next - dc->cs_base); + /* The address covered by the breakpoint must be included in + [tb->pc, tb->pc + tb->size) in order to for it to be + properly cleared -- thus we increment the PC here so that + the logic setting tb->size below does the right thing. */ + db->pc_next += 1; + return BC_HIT_TB; + } else { + return BC_MISS; + } +} + /* generate intermediate code for basic block 'tb'. */ void gen_intermediate_code(CPUState *cpu, TranslationBlock *tb) { CPUX86State *env = cpu->env_ptr; DisasContext dc1, *dc = &dc1; DisasContextBase *db = &dc1.base; + CPUBreakpoint *bp; int num_insns; int max_insns; @@ -8507,18 +8528,21 @@ void gen_intermediate_code(CPUState *cpu, TranslationBlock *tb) i386_trblock_insn_start(db, cpu); num_insns++; - /* If RF is set, suppress an internally generated breakpoint. */ - if (unlikely(cpu_breakpoint_test(cpu, db->pc_next, - tb->flags & HF_RF_MASK - ? BP_GDB : BP_ANY))) { - gen_debug(dc, db->pc_next - dc->cs_base); - /* The address covered by the breakpoint must be included in - [tb->pc, tb->pc + tb->size) in order to for it to be - properly cleared -- thus we increment the PC here so that - the logic setting tb->size below does the right thing. */ - db->pc_next += 1; - goto done_generating; - } + bp = NULL; + do { + bp = cpu_breakpoint_get(cpu, db->pc_next, bp); + if (unlikely(bp)) { + BreakpointCheckType bp_check = i386_trblock_breakpoint_check( + db, cpu, bp); + if (bp_check == BC_HIT_TB) { + goto done_generating; + } else { + error_report("Unexpected BreakpointCheckType %d", bp_check); + abort(); + } + } + } while (bp != NULL); + if (num_insns == max_insns && (tb->cflags & CF_LAST_IO)) { gen_io_start(cpu_env); }