From patchwork Thu Jun 22 17:46:50 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Llu=C3=ADs_Vilanova?= X-Patchwork-Id: 779652 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3wtpvv4gxzz9sNv for ; Fri, 23 Jun 2017 03:48:11 +1000 (AEST) Received: from localhost ([::1]:60280 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dO6DB-0001eB-9Q for incoming@patchwork.ozlabs.org; Thu, 22 Jun 2017 13:48:09 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:39760) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dO6C8-0001LY-PI for qemu-devel@nongnu.org; Thu, 22 Jun 2017 13:47:06 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dO6C4-0000oG-An for qemu-devel@nongnu.org; Thu, 22 Jun 2017 13:47:04 -0400 Received: from roura.ac.upc.edu ([147.83.33.10]:44875 helo=roura.ac.upc.es) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dO6C3-0000o5-V1 for qemu-devel@nongnu.org; Thu, 22 Jun 2017 13:47:00 -0400 Received: from correu-2.ac.upc.es (correu-2.ac.upc.es [147.83.30.92]) by roura.ac.upc.es (8.13.8/8.13.8) with ESMTP id v5MHkvin009938; Thu, 22 Jun 2017 19:46:57 +0200 Received: from localhost (unknown [31.210.182.235]) by correu-2.ac.upc.es (Postfix) with ESMTPSA id B6DE8880; Thu, 22 Jun 2017 19:46:51 +0200 (CEST) From: =?utf-8?b?TGx1w61z?= Vilanova To: qemu-devel@nongnu.org Date: Thu, 22 Jun 2017 20:46:50 +0300 Message-Id: <149815361027.1830.12938924682989954179.stgit@frigg.lan> X-Mailer: git-send-email 2.11.0 In-Reply-To: <149815338558.1830.8107719559183631163.stgit@frigg.lan> References: <149815338558.1830.8107719559183631163.stgit@frigg.lan> User-Agent: StGit/0.17.1-dirty MIME-Version: 1.0 X-MIME-Autoconverted: from 8bit to quoted-printable by roura.ac.upc.es id v5MHkvin009938 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.6.x [fuzzy] X-Received-From: 147.83.33.10 Subject: [Qemu-devel] [PATCH v7 07/26] target: [tcg, i386] Refactor init_disas_context X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Paolo Bonzini , Peter Crosthwaite , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Eduardo Habkost , Richard Henderson Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Incrementally paves the way towards using the generic instruction translation loop. Signed-off-by: Lluís Vilanova --- target/i386/translate.c | 43 ++++++++++++++++++++++++------------------- 1 file changed, 24 insertions(+), 19 deletions(-) diff --git a/target/i386/translate.c b/target/i386/translate.c index 5a801766e5..84ff49030b 100644 --- a/target/i386/translate.c +++ b/target/i386/translate.c @@ -8396,21 +8396,12 @@ void tcg_x86_init(void) } } -/* generate intermediate code for basic block 'tb'. */ -void gen_intermediate_code(CPUState *cpu, TranslationBlock *tb) +static void i386_trblock_init_disas_context(DisasContextBase *db, CPUState *cpu) { + DisasContext *dc = container_of(db, DisasContext, base); CPUX86State *env = cpu->env_ptr; - DisasContext dc1, *dc = &dc1; - DisasContextBase *db = &dc1.base; - uint32_t flags; - target_ulong cs_base; - int num_insns; - int max_insns; - - /* generate intermediate code */ - db->pc_first = tb->pc; - cs_base = tb->cs_base; - flags = tb->flags; + uint32_t flags = db->tb->flags; + target_ulong cs_base = db->tb->cs_base; dc->pe = (flags >> HF_PE_SHIFT) & 1; dc->code32 = (flags >> HF_CS32_SHIFT) & 1; @@ -8421,11 +8412,9 @@ void gen_intermediate_code(CPUState *cpu, TranslationBlock *tb) dc->cpl = (flags >> HF_CPL_SHIFT) & 3; dc->iopl = (flags >> IOPL_SHIFT) & 3; dc->tf = (flags >> TF_SHIFT) & 1; - db->singlestep_enabled = cpu->singlestep_enabled; dc->cc_op = CC_OP_DYNAMIC; dc->cc_op_dirty = false; dc->cs_base = cs_base; - db->tb = tb; dc->popl_esp_hack = 0; /* select memory access functions */ dc->mem_index = 0; @@ -8455,12 +8444,30 @@ void gen_intermediate_code(CPUState *cpu, TranslationBlock *tb) record/replay modes and there will always be an additional step for ecx=0 when icount is enabled. */ - dc->repz_opt = !dc->jmp_opt && !(tb->cflags & CF_USE_ICOUNT); + dc->repz_opt = !dc->jmp_opt && !(db->tb->cflags & CF_USE_ICOUNT); #if 0 /* check addseg logic */ if (!dc->addseg && (dc->vm86 || !dc->pe || !dc->code32)) printf("ERROR addseg\n"); #endif +} + +/* generate intermediate code for basic block 'tb'. */ +void gen_intermediate_code(CPUState *cpu, TranslationBlock *tb) +{ + CPUX86State *env = cpu->env_ptr; + DisasContext dc1, *dc = &dc1; + DisasContextBase *db = &dc1.base; + int num_insns; + int max_insns; + + /* generate intermediate code */ + db->singlestep_enabled = cpu->singlestep_enabled; + db->tb = tb; + db->is_jmp = DISAS_NEXT; + db->pc_first = tb->pc; + db->pc_next = db->pc_first; + i386_trblock_init_disas_context(db, cpu); cpu_T0 = tcg_temp_new(); cpu_T1 = tcg_temp_new(); @@ -8475,8 +8482,6 @@ void gen_intermediate_code(CPUState *cpu, TranslationBlock *tb) cpu_ptr1 = tcg_temp_new_ptr(); cpu_cc_srcT = tcg_temp_local_new(); - db->is_jmp = DISAS_NEXT; - db->pc_next = db->pc_first; num_insns = 0; max_insns = tb->cflags & CF_COUNT_MASK; if (max_insns == 0) { @@ -8518,7 +8523,7 @@ void gen_intermediate_code(CPUState *cpu, TranslationBlock *tb) the flag and abort the translation to give the irqs a change to be happen */ if (dc->tf || db->singlestep_enabled || - (flags & HF_INHIBIT_IRQ_MASK)) { + (db->tb->flags & HF_INHIBIT_IRQ_MASK)) { gen_jmp_im(db->pc_next - dc->cs_base); gen_eob(dc); break;