From patchwork Tue May 30 16:39:35 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 768719 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3wcfV04gwSz9s2P for ; Wed, 31 May 2017 02:40:08 +1000 (AEST) Received: from localhost ([::1]:55019 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dFkBi-0007LW-9l for incoming@patchwork.ozlabs.org; Tue, 30 May 2017 12:40:06 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:37170) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dFkBQ-0007LN-7Z for qemu-devel@nongnu.org; Tue, 30 May 2017 12:39:49 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dFkBP-0003uI-6e for qemu-devel@nongnu.org; Tue, 30 May 2017 12:39:48 -0400 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:37133) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1dFkBO-0003s6-Rf for qemu-devel@nongnu.org; Tue, 30 May 2017 12:39:47 -0400 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.84_2) (envelope-from ) id 1dFkBE-0005PZ-SB; Tue, 30 May 2017 17:39:36 +0100 From: Peter Maydell To: qemu-devel@nongnu.org Date: Tue, 30 May 2017 17:39:35 +0100 Message-Id: <1496162375-1571-1-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 2.7.4 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PATCH risu] ppc64.risu: Fix broken constraints X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?q?Alex=20Benn=C3=A9e?= , Sandipan Das , Jose Ricardo Ziviani , Nikunj A Dadhania , patches@linaro.org Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Commit c10b97092 changed some field names in rldicr and rldimi patterns but forgot to update the constraints to match the change. Since the field (previously 'rb' and now 'sh') is an immediate rather than a register number, the correct fix is to just delete the constraint since we don't need to avoid particular values. Signed-off-by: Peter Maydell --- ppc64.risu | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/ppc64.risu b/ppc64.risu index dd304e2..e2fd4f6 100644 --- a/ppc64.risu +++ b/ppc64.risu @@ -1473,17 +1473,17 @@ RLDICLd PPC64LE 011110 rs:5 ra:5 sh:5 mb:6 000 sha:1 1 \ # format:MD book:I page:105 PPC SR rldicr[.] Rotate Left Dword Immediate then Clear Right RLDICR PPC64LE 011110 rs:5 ra:5 sh:5 me:6 001 sha:1 0 \ -!constraints { $rs != 1 && $ra != 1 && $rb != 1 && $rs != 13 && $ra != 13 && $rb != 13; } +!constraints { $rs != 1 && $ra != 1 && $rs != 13 && $ra != 13; } # format:MD book:I page:105 PPC SR rldicr[.] Rotate Left Dword Immediate then Clear Right RLDICRd PPC64LE 011110 rs:5 ra:5 sh:5 me:6 001 sha:1 1 \ -!constraints { $rs != 1 && $ra != 1 && $rb != 1 && $rs != 13 && $ra != 13 && $rb != 13; } +!constraints { $rs != 1 && $ra != 1 && $rs != 13 && $ra != 13; } # format:MD book:I page:105 PPC SR rldimi[.] Rotate Left Dword Immediate then Mask Insert RLDIMI PPC64LE 011110 rs:5 ra:5 sh:5 me:6 011 sha:1 0 \ -!constraints { $rs != 1 && $ra != 1 && $rb != 1 && $rs != 13 && $ra != 13 && $rb != 13; } +!constraints { $rs != 1 && $ra != 1 && $rs != 13 && $ra != 13; } # format:MD book:I page:105 PPC SR rldimi[.] Rotate Left Dword Immediate then Mask Insert RLDIMId PPC64LE 011110 rs:5 ra:5 sh:5 me:6 011 sha:1 1 \ -!constraints { $rs != 1 && $ra != 1 && $rb != 1 && $rs != 13 && $ra != 13 && $rb != 13; } +!constraints { $rs != 1 && $ra != 1 && $rs != 13 && $ra != 13; } # format:M book:I page:102 v:P1 SR rlwimi[.] Rotate Left Word Immediate then Mask Insert RLWIMI PPC64LE 010100 rs:5 ra:5 sh:5 mb:5 me:5 0 \