From patchwork Mon Feb 20 04:04:31 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Suraj Jitindar Singh X-Patchwork-Id: 729708 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3vRVYw4rZRz9s8G for ; Mon, 20 Feb 2017 15:11:31 +1100 (AEDT) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="moMKIRYH"; dkim-atps=neutral Received: from localhost ([::1]:36000 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1cffJw-0005w4-DS for incoming@patchwork.ozlabs.org; Sun, 19 Feb 2017 23:11:28 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:39792) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1cffDi-0000AI-TV for qemu-devel@nongnu.org; Sun, 19 Feb 2017 23:05:04 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1cffDh-0002Zj-Rh for qemu-devel@nongnu.org; Sun, 19 Feb 2017 23:05:02 -0500 Received: from mail-pg0-x243.google.com ([2607:f8b0:400e:c05::243]:33649) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1cffDd-0002Wz-IS; Sun, 19 Feb 2017 23:04:57 -0500 Received: by mail-pg0-x243.google.com with SMTP id 5so11171573pgj.0; Sun, 19 Feb 2017 20:04:57 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=PzhvIcrBi9btcPVpigl/k+BtcF450gg0JR7bQDRAdiY=; b=moMKIRYHEJ7oVtg3CHbOXUTatyo5mFFJyCNz77HLYz8fcNK/Yd+SIb6fxok0bSvHuG /amtPGFZzZkzX5D2VOC6uRirCP1T09oX9V18cgFu1y1/dnBPrsrOFqE0cnOGQiBfPOpB gfXgBa2icFvaezTGs/hS1e8KqX5XS10u8uS5TdsNIZ3T98iyGi5L0NHAcbc54rGhsn6H lHePH54RcYQX80SYovjXSuQP6InrFYNXQv97fenMsucBCSOBf1p8MCSoopCyOcIhzOoY uL2razn5GleIV8j4PTLlmdDU6i1vJP1AE1jbb8NIk7J4KqiA1xor+zn/+ipqLMFri/vw d+4w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=PzhvIcrBi9btcPVpigl/k+BtcF450gg0JR7bQDRAdiY=; b=VGyyRVwB7u7EIzvrpQK3AJ91mCdiNo6mkX4fDPhYneLcZOtipKNChy2iedJeTahfKM 3ljy0qMK/uxI7Ec1slsvithRbA/xn6l9c/mjSRP7CO6pigrQ+0SEF92DJvilj0S3Ll4U BtY4Bmw0HjNgxqjGpx9vdLsZ5tyBcZFYTSWeFJm+9VKpXfvbd9dPkT5jpBViyaPHJgok BrSJzO/7gFo3OR7pQmEkN2syxdMkSFtqQozBCi4vemsDnltnQMspojv0Uq0Wp4heUmQJ LJMzuknXF7V64W0VzfuTyDRFgZZgDqUzLPtWb4wyQE18/ztWz9+lFUqM8M1X22vXEzrD vKHA== X-Gm-Message-State: AMke39ngMLp37gvMdvOA25f31Drz6LwjIAzjVnCH4Z0XbVxUOE4EzflIrdLvAk8/mlUybw== X-Received: by 10.99.167.10 with SMTP id d10mr25023103pgf.19.1487563496567; Sun, 19 Feb 2017 20:04:56 -0800 (PST) Received: from surajjs.ozlabs.ibm.com ([122.99.82.10]) by smtp.gmail.com with ESMTPSA id d78sm31622707pfb.43.2017.02.19.20.04.53 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sun, 19 Feb 2017 20:04:56 -0800 (PST) From: Suraj Jitindar Singh To: qemu-ppc@nongnu.org Date: Mon, 20 Feb 2017 15:04:31 +1100 Message-Id: <1487563478-22265-4-git-send-email-sjitindarsingh@gmail.com> X-Mailer: git-send-email 2.5.5 In-Reply-To: <1487563478-22265-1-git-send-email-sjitindarsingh@gmail.com> References: <1487563478-22265-1-git-send-email-sjitindarsingh@gmail.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 2607:f8b0:400e:c05::243 Subject: [Qemu-devel] [QEMU-PPC] [PATCH V3 03/10] target/ppc/POWER9: Adapt LPCR handling for POWER9 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-devel@nongnu.org, sjitindarsingh@gmail.com, agraf@suse.de, sam.bobroff@au1.ibm.com, david@gibson.dropbear.id.au Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" The logical partitioning control register controls a threads operation based on the partition it is currently executing. Add new definitions and update the mask used when writing to the LPCR based on the POWER9 spec. Signed-off-by: Suraj Jitindar Singh Reviewed-by: David Gibson --- target/ppc/cpu.h | 18 ++++++++++++++++++ target/ppc/mmu-hash64.c | 8 ++++++++ target/ppc/translate_init.c | 24 ++++++++++++++++++------ 3 files changed, 44 insertions(+), 6 deletions(-) diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index bb96dd5..425e79d 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -384,12 +384,19 @@ struct ppc_slb_t { #define LPCR_DPFD (0x7ull << LPCR_DPFD_SHIFT) #define LPCR_VRMASD_SHIFT (63 - 16) #define LPCR_VRMASD (0x1full << LPCR_VRMASD_SHIFT) +/* P9: Power-saving mode Exit Cause Enable (Upper Section) Mask */ +#define LPCR_PECE_U_SHIFT (63 - 19) +#define LPCR_PECE_U_MASK (0x7ull << LPCR_PECE_U_SHIFT) +#define LPCR_HVEE (1ull << (63 - 17)) /* Hypervisor Virt Exit Enable */ #define LPCR_RMLS_SHIFT (63 - 37) #define LPCR_RMLS (0xfull << LPCR_RMLS_SHIFT) #define LPCR_ILE (1ull << (63 - 38)) #define LPCR_AIL_SHIFT (63 - 40) /* Alternate interrupt location */ #define LPCR_AIL (3ull << LPCR_AIL_SHIFT) +#define LPCR_UPRT (1ull << (63 - 41)) /* Use Process Table */ +#define LPCR_EVIRT (1ull << (63 - 42)) /* Enhanced Virtualisation */ #define LPCR_ONL (1ull << (63 - 45)) +#define LPCR_LD (1ull << (63 - 46)) /* Large Decrementer */ #define LPCR_P7_PECE0 (1ull << (63 - 49)) #define LPCR_P7_PECE1 (1ull << (63 - 50)) #define LPCR_P7_PECE2 (1ull << (63 - 51)) @@ -398,11 +405,22 @@ struct ppc_slb_t { #define LPCR_P8_PECE2 (1ull << (63 - 49)) #define LPCR_P8_PECE3 (1ull << (63 - 50)) #define LPCR_P8_PECE4 (1ull << (63 - 51)) +/* P9: Power-saving mode Exit Cause Enable (Lower Section) Mask */ +#define LPCR_PECE_L_SHIFT (63 - 51) +#define LPCR_PECE_L_MASK (0x1full << LPCR_PECE_L_SHIFT) +#define LPCR_PDEE (1ull << (63 - 47)) /* Privileged Doorbell Exit EN */ +#define LPCR_HDEE (1ull << (63 - 48)) /* Hyperv Doorbell Exit Enable */ +#define LPCR_EEE (1ull << (63 - 49)) /* External Exit Enable */ +#define LPCR_DEE (1ull << (63 - 50)) /* Decrementer Exit Enable */ +#define LPCR_OEE (1ull << (63 - 51)) /* Other Exit Enable */ #define LPCR_MER (1ull << (63 - 52)) +#define LPCR_GTSE (1ull << (63 - 53)) /* Guest Translation Shootdown */ #define LPCR_TC (1ull << (63 - 54)) +#define LPCR_HEIC (1ull << (63 - 59)) /* HV Extern Interrupt Control */ #define LPCR_LPES0 (1ull << (63 - 60)) #define LPCR_LPES1 (1ull << (63 - 61)) #define LPCR_RMI (1ull << (63 - 62)) +#define LPCR_HVICE (1ull << (63 - 62)) /* HV Virtualisation Int Enable */ #define LPCR_HDICE (1ull << (63 - 63)) #define msr_sf ((env->msr >> MSR_SF) & 1) diff --git a/target/ppc/mmu-hash64.c b/target/ppc/mmu-hash64.c index bb78fb5..24d9901 100644 --- a/target/ppc/mmu-hash64.c +++ b/target/ppc/mmu-hash64.c @@ -1050,6 +1050,14 @@ void helper_store_lpcr(CPUPPCState *env, target_ulong val) LPCR_P8_PECE2 | LPCR_P8_PECE3 | LPCR_P8_PECE4 | LPCR_MER | LPCR_TC | LPCR_LPES0 | LPCR_HDICE); break; + case POWERPC_MMU_3_00: /* P9 */ + lpcr = val & (LPCR_VPM1 | LPCR_ISL | LPCR_KBV | LPCR_DPFD | + (LPCR_PECE_U_MASK & LPCR_HVEE) | LPCR_ILE | LPCR_AIL | + LPCR_UPRT | LPCR_EVIRT | LPCR_ONL | + (LPCR_PECE_L_MASK & (LPCR_PDEE | LPCR_HDEE | LPCR_EEE | + LPCR_DEE | LPCR_OEE)) | LPCR_MER | LPCR_GTSE | LPCR_TC | + LPCR_HEIC | LPCR_LPES0 | LPCR_HVICE | LPCR_HDICE); + break; default: ; } diff --git a/target/ppc/translate_init.c b/target/ppc/translate_init.c index 84bf125..be35cbd 100644 --- a/target/ppc/translate_init.c +++ b/target/ppc/translate_init.c @@ -8870,12 +8870,24 @@ void cpu_ppc_set_papr(PowerPCCPU *cpu) lpcr->default_value &= ~LPCR_RMLS; lpcr->default_value |= 1ull << LPCR_RMLS_SHIFT; - /* P7 and P8 has slightly different PECE bits, mostly because P8 adds - * bit 47 and 48 which are reserved on P7. Here we set them all, which - * will work as expected for both implementations - */ - lpcr->default_value |= LPCR_P8_PECE0 | LPCR_P8_PECE1 | LPCR_P8_PECE2 | - LPCR_P8_PECE3 | LPCR_P8_PECE4; + switch (env->mmu_model) { + case POWERPC_MMU_3_00: + /* By default we choose legacy mode and switch to new hash or radix + * when a register process table hcall is made. So disable process + * tables and guest translation shootdown by default + */ + lpcr->default_value &= ~(LPCR_UPRT | LPCR_GTSE); + lpcr->default_value |= LPCR_PDEE | LPCR_HDEE | LPCR_EEE | LPCR_DEE | + LPCR_OEE; + break; + default: + /* P7 and P8 has slightly different PECE bits, mostly because P8 adds + * bit 47 and 48 which are reserved on P7. Here we set them all, which + * will work as expected for both implementations + */ + lpcr->default_value |= LPCR_P8_PECE0 | LPCR_P8_PECE1 | LPCR_P8_PECE2 | + LPCR_P8_PECE3 | LPCR_P8_PECE4; + } /* We should be followed by a CPU reset but update the active value * just in case...