From patchwork Tue Feb 7 21:49:31 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Wei Huang X-Patchwork-Id: 725381 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3vHyqg0Nh4z9s4s for ; Wed, 8 Feb 2017 08:57:19 +1100 (AEDT) Received: from localhost ([::1]:56575 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1cbDlE-0000Vv-J7 for incoming@patchwork.ozlabs.org; Tue, 07 Feb 2017 16:57:16 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:48937) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1cbDdq-0002zT-9V for qemu-devel@nongnu.org; Tue, 07 Feb 2017 16:49:39 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1cbDdp-0007cp-5a for qemu-devel@nongnu.org; Tue, 07 Feb 2017 16:49:38 -0500 Received: from mx1.redhat.com ([209.132.183.28]:56024) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1cbDdm-0007YP-Cm; Tue, 07 Feb 2017 16:49:34 -0500 Received: from int-mx09.intmail.prod.int.phx2.redhat.com (int-mx09.intmail.prod.int.phx2.redhat.com [10.5.11.22]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id 74018C05AA42; Tue, 7 Feb 2017 21:49:34 +0000 (UTC) Received: from apm-mustang-ev3-30.khw.lab.eng.bos.redhat.com (apm-mustang-ev3-30.khw.lab.eng.bos.redhat.com [10.16.184.124]) by int-mx09.intmail.prod.int.phx2.redhat.com (8.14.4/8.14.4) with ESMTP id v17LnVCJ006452; Tue, 7 Feb 2017 16:49:34 -0500 From: Wei Huang To: qemu-devel@nongnu.org Date: Tue, 7 Feb 2017 16:49:31 -0500 Message-Id: <1486504171-26807-5-git-send-email-wei@redhat.com> In-Reply-To: <1486504171-26807-1-git-send-email-wei@redhat.com> References: <1486504171-26807-1-git-send-email-wei@redhat.com> X-Scanned-By: MIMEDefang 2.68 on 10.5.11.22 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.32]); Tue, 07 Feb 2017 21:49:34 +0000 (UTC) X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.132.183.28 Subject: [Qemu-devel] [PATCH V3 4/4] target-arm: Enable vPMU support under TCG mode X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" This patch contains several fixes to enable vPMU under TCG mode. It first removes the checking of kvm_enabled() while unsetting ARM_FEATURE_PMU. With it, the .pmu option can be used to turn on/off vPMU under TCG mode. Secondly the PMU node of DT table is now created under TCG. The last fix is to disable the masking of PMUver field of ID_AA64DFR0_EL1. Signed-off-by: Wei Huang Reviewed-by: Peter Maydell --- hw/arm/virt.c | 2 +- target/arm/cpu.c | 2 +- target/arm/helper.c | 7 +------ 3 files changed, 3 insertions(+), 8 deletions(-) diff --git a/hw/arm/virt.c b/hw/arm/virt.c index 1f216cf..8eef143 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -471,7 +471,7 @@ static void fdt_add_pmu_nodes(const VirtMachineState *vms) CPU_FOREACH(cpu) { armcpu = ARM_CPU(cpu); if (!arm_feature(&armcpu->env, ARM_FEATURE_PMU) || - !kvm_arm_pmu_create(cpu, PPI(VIRTUAL_PMU_IRQ))) { + (kvm_enabled() && !kvm_arm_pmu_create(cpu, PPI(VIRTUAL_PMU_IRQ)))) { return; } } diff --git a/target/arm/cpu.c b/target/arm/cpu.c index e9f10f7..9a2bc8a 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -745,7 +745,7 @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp) unset_feature(env, ARM_FEATURE_EL2); } - if (!cpu->has_pmu || !kvm_enabled()) { + if (!cpu->has_pmu) { cpu->has_pmu = false; unset_feature(env, ARM_FEATURE_PMU); } diff --git a/target/arm/helper.c b/target/arm/helper.c index c4daa6e..d363d02 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -4633,12 +4633,7 @@ void register_cp_regs_for_features(ARMCPU *cpu) { .name = "ID_AA64DFR0_EL1", .state = ARM_CP_STATE_AA64, .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 0, .access = PL1_R, .type = ARM_CP_CONST, - /* We mask out the PMUVer field, because we don't currently - * implement the PMU. Not advertising it prevents the guest - * from trying to use it and getting UNDEFs on registers we - * don't implement. - */ - .resetvalue = cpu->id_aa64dfr0 & ~0xf00 }, + .resetvalue = cpu->id_aa64dfr0 }, { .name = "ID_AA64DFR1_EL1", .state = ARM_CP_STATE_AA64, .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 1, .access = PL1_R, .type = ARM_CP_CONST,