From patchwork Thu Feb 2 14:34:47 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kirill Batuzov X-Patchwork-Id: 723053 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3vDjRk11xmz9s7B for ; Fri, 3 Feb 2017 01:43:46 +1100 (AEDT) Received: from localhost ([::1]:57018 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1cZIbv-0004jk-Ij for incoming@patchwork.ozlabs.org; Thu, 02 Feb 2017 09:43:43 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:35230) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1cZIU1-0005Ki-26 for qemu-devel@nongnu.org; Thu, 02 Feb 2017 09:35:36 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1cZITx-0005Pb-Co for qemu-devel@nongnu.org; Thu, 02 Feb 2017 09:35:33 -0500 Received: from bran.ispras.ru ([83.149.199.196]:39800 helo=smtp.ispras.ru) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1cZITx-0005OW-5L for qemu-devel@nongnu.org; Thu, 02 Feb 2017 09:35:29 -0500 Received: from bulbul.intra.ispras.ru (spartak.intra.ispras.ru [10.10.3.51]) by smtp.ispras.ru (Postfix) with ESMTP id 4FEFF612D5; Thu, 2 Feb 2017 17:35:28 +0300 (MSK) From: Kirill Batuzov To: qemu-devel@nongnu.org Date: Thu, 2 Feb 2017 17:34:47 +0300 Message-Id: <1486046099-17726-10-git-send-email-batuzovk@ispras.ru> X-Mailer: git-send-email 2.1.4 In-Reply-To: <1486046099-17726-1-git-send-email-batuzovk@ispras.ru> References: <1486046099-17726-1-git-send-email-batuzovk@ispras.ru> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [fuzzy] X-Received-From: 83.149.199.196 Subject: [Qemu-devel] [PATCH v2.1 09/21] target/arm: support access to vector guest registers as globals X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , Peter Crosthwaite , Kirill Batuzov , Paolo Bonzini , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Richard Henderson Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" To support vector guest registers as globals we need to do two things: 1) create corresponding globals, 2) mark which globals can overlap, Signed-off-by: Kirill Batuzov --- For vector registers I used the same coding style as was used for scalar registers. Should I change braces placement for them all? --- target/arm/translate.c | 30 ++++++++++++++++++++++++++++-- 1 file changed, 28 insertions(+), 2 deletions(-) diff --git a/target/arm/translate.c b/target/arm/translate.c index 493c627..d7578e2 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -65,6 +65,8 @@ static TCGv_i32 cpu_R[16]; TCGv_i32 cpu_CF, cpu_NF, cpu_VF, cpu_ZF; TCGv_i64 cpu_exclusive_addr; TCGv_i64 cpu_exclusive_val; +static TCGv_v128 cpu_Q[16]; +static TCGv_v64 cpu_D[32]; /* FIXME: These should be removed. */ static TCGv_i32 cpu_F0s, cpu_F1s; @@ -72,10 +74,20 @@ static TCGv_i64 cpu_F0d, cpu_F1d; #include "exec/gen-icount.h" -static const char *regnames[] = +static const char *regnames_r[] = { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12", "r13", "r14", "pc" }; +static const char *regnames_q[] = + { "q0", "q1", "q2", "q3", "q4", "q5", "q6", "q7", + "q8", "q9", "q10", "q11", "q12", "q13", "q14", "q15" }; + +static const char *regnames_d[] = + { "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7", + "d8", "d9", "d10", "d11", "d12", "d13", "d14", "d15", + "d16", "d17", "d18", "d19", "d20", "d21", "d22", "d23", + "d24", "d25", "d26", "d27", "d28", "d29", "d30", "d31" }; + /* initialize TCG globals. */ void arm_translate_init(void) { @@ -87,8 +99,22 @@ void arm_translate_init(void) for (i = 0; i < 16; i++) { cpu_R[i] = tcg_global_mem_new_i32(cpu_env, offsetof(CPUARMState, regs[i]), - regnames[i]); + regnames_r[i]); + } + for (i = 0; i < 16; i++) { + cpu_Q[i] = tcg_global_mem_new_v128(cpu_env, + offsetof(CPUARMState, + vfp.regs[2 * i]), + regnames_q[i]); } + for (i = 0; i < 32; i++) { + cpu_D[i] = tcg_global_mem_new_v64(cpu_env, + offsetof(CPUARMState, vfp.regs[i]), + regnames_d[i]); + } + + tcg_detect_overlapping_temps(&tcg_ctx); + cpu_CF = tcg_global_mem_new_i32(cpu_env, offsetof(CPUARMState, CF), "CF"); cpu_NF = tcg_global_mem_new_i32(cpu_env, offsetof(CPUARMState, NF), "NF"); cpu_VF = tcg_global_mem_new_i32(cpu_env, offsetof(CPUARMState, VF), "VF");