From patchwork Fri Jan 13 03:54:08 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nikunj A Dadhania X-Patchwork-Id: 714773 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3v081Q6ccdz9svs for ; Fri, 13 Jan 2017 14:55:54 +1100 (AEDT) Received: from localhost ([::1]:38929 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1cRsy0-0006D7-Ha for incoming@patchwork.ozlabs.org; Thu, 12 Jan 2017 22:55:52 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:57643) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1cRswt-0005U4-Og for qemu-devel@nongnu.org; Thu, 12 Jan 2017 22:54:46 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1cRswq-0003u1-L4 for qemu-devel@nongnu.org; Thu, 12 Jan 2017 22:54:43 -0500 Received: from mx0a-001b2d01.pphosted.com ([148.163.156.1]:59412) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1cRswq-0003tq-BW for qemu-devel@nongnu.org; Thu, 12 Jan 2017 22:54:40 -0500 Received: from pps.filterd (m0098394.ppops.net [127.0.0.1]) by mx0a-001b2d01.pphosted.com (8.16.0.17/8.16.0.17) with SMTP id v0D3s44w048179 for ; Thu, 12 Jan 2017 22:54:39 -0500 Received: from e23smtp03.au.ibm.com (e23smtp03.au.ibm.com [202.81.31.145]) by mx0a-001b2d01.pphosted.com with ESMTP id 27xpvm0ug5-1 (version=TLSv1.2 cipher=AES256-SHA bits=256 verify=NOT) for ; Thu, 12 Jan 2017 22:54:39 -0500 Received: from localhost by e23smtp03.au.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! 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Violators will be prosecuted; Fri, 13 Jan 2017 13:54:34 +1000 Received: from d23relay07.au.ibm.com (d23relay07.au.ibm.com [9.190.26.37]) by d23dlp03.au.ibm.com (Postfix) with ESMTP id A248E3578056; Fri, 13 Jan 2017 14:54:33 +1100 (EST) Received: from d23av04.au.ibm.com (d23av04.au.ibm.com [9.190.235.139]) by d23relay07.au.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id v0D3sXQ523527646; Fri, 13 Jan 2017 14:54:33 +1100 Received: from d23av04.au.ibm.com (localhost [127.0.0.1]) by d23av04.au.ibm.com (8.14.4/8.14.4/NCO v10.0 AVout) with ESMTP id v0D3sXBd001216; Fri, 13 Jan 2017 14:54:33 +1100 Received: from abhimanyu.in.ibm.com ([9.85.83.176]) by d23av04.au.ibm.com (8.14.4/8.14.4/NCO v10.0 AVin) with ESMTP id v0D3sKot000935; Fri, 13 Jan 2017 14:54:28 +1100 From: Nikunj A Dadhania To: qemu-ppc@nongnu.org, david@gibson.dropbear.id.au, rth@twiddle.net Date: Fri, 13 Jan 2017 09:24:08 +0530 X-Mailer: git-send-email 2.7.4 In-Reply-To: <1484279649-22286-1-git-send-email-nikunj@linux.vnet.ibm.com> References: <1484279649-22286-1-git-send-email-nikunj@linux.vnet.ibm.com> X-TM-AS-MML: disable X-Content-Scanned: Fidelis XPS MAILER x-cbid: 17011303-0008-0000-0000-000000FC5208 X-IBM-AV-DETECTION: SAVI=unused REMOTE=unused XFE=unused x-cbparentid: 17011303-0009-0000-0000-000008DE90E6 Message-Id: <1484279649-22286-2-git-send-email-nikunj@linux.vnet.ibm.com> X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10432:, , definitions=2017-01-12_16:, , signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 suspectscore=0 malwarescore=0 phishscore=0 adultscore=0 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1612050000 definitions=main-1701130052 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [generic] [fuzzy] X-Received-From: 148.163.156.1 Subject: [Qemu-devel] [PATCH v1 1/2] target-ppc: Add xvtstdc[sp, dp] instructions X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-devel@nongnu.org, nikunj@linux.vnet.ibm.com, bharata@linux.vnet.ibm.com Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" xvtstdcsp: VSX Vector Test Data Class Single-Precision xvtstdcdp: VSX Vector Test Data Class Double-Precision Signed-off-by: Nikunj A Dadhania --- target/ppc/fpu_helper.c | 39 +++++++++++++++++++++++++++++++++++++ target/ppc/helper.h | 2 ++ target/ppc/internal.h | 5 +++-- target/ppc/translate/vsx-impl.inc.c | 2 ++ target/ppc/translate/vsx-ops.inc.c | 8 ++++++++ 5 files changed, 54 insertions(+), 2 deletions(-) diff --git a/target/ppc/fpu_helper.c b/target/ppc/fpu_helper.c index ffcf9ca..75c70e4 100644 --- a/target/ppc/fpu_helper.c +++ b/target/ppc/fpu_helper.c @@ -3187,3 +3187,42 @@ void helper_xvxsigsp(CPUPPCState *env, uint32_t opcode) } putVSR(xT(opcode), &xt, env); } + +/* VSX_TEST_DC - VSX floating point test data class + * op - instruction mnemonic + * nels - number of elements (1, 2 or 4) + * xbn - VSR register number + * tp - type (float32 or float64) + * fld - vsr_t field (VsrD(*) or VsrW(*)) + * tfld - target vsr_t field (VsrD(*) or VsrW(*)) + * fld_max - target field max + */ +#define VSX_TEST_DC(op, nels, xbn, tp, fld, tfld, fld_max) \ +void helper_##op(CPUPPCState *env, uint32_t opcode) \ +{ \ + ppc_vsr_t xt, xb; \ + uint32_t i, sign, dcmx; \ + uint32_t match = 0; \ + \ + getVSR(xbn, &xb, env); \ + memset(&xt, 0, sizeof(xt)); \ + dcmx = DCMX_XV(opcode); \ + \ + for (i = 0; i < nels; i++) { \ + sign = tp##_is_neg(xb.fld); \ + if (tp##_is_any_nan(xb.fld)) { \ + match = extract32(dcmx, 6, 1); \ + } else if (tp##_is_infinity(xb.fld)) { \ + match = extract32(dcmx, 4 + !sign, 1); \ + } else if (tp##_is_zero(xb.fld)) { \ + match = extract32(dcmx, 2 + !sign, 1); \ + } else if (tp##_is_zero_or_denormal(xb.fld)) { \ + match = extract32(dcmx, 0 + !sign, 1); \ + } \ + xt.tfld = match ? fld_max : 0; \ + } \ + putVSR(xT(opcode), &xt, env); \ +} + +VSX_TEST_DC(xvtstdcdp, 2, xB(opcode), float64, VsrD(i), VsrD(i), UINT64_MAX) +VSX_TEST_DC(xvtstdcsp, 4, xB(opcode), float32, VsrW(i), VsrW(i), UINT32_MAX) diff --git a/target/ppc/helper.h b/target/ppc/helper.h index 9d4ed08..165e4a5 100644 --- a/target/ppc/helper.h +++ b/target/ppc/helper.h @@ -546,6 +546,8 @@ DEF_HELPER_2(xvcvsxdsp, void, env, i32) DEF_HELPER_2(xvcvuxdsp, void, env, i32) DEF_HELPER_2(xvcvsxwsp, void, env, i32) DEF_HELPER_2(xvcvuxwsp, void, env, i32) +DEF_HELPER_2(xvtstdcsp, void, env, i32) +DEF_HELPER_2(xvtstdcdp, void, env, i32) DEF_HELPER_2(xvrspi, void, env, i32) DEF_HELPER_2(xvrspic, void, env, i32) DEF_HELPER_2(xvrspim, void, env, i32) diff --git a/target/ppc/internal.h b/target/ppc/internal.h index c22d74e..4c3811a 100644 --- a/target/ppc/internal.h +++ b/target/ppc/internal.h @@ -68,7 +68,7 @@ static inline uint32_t name(uint32_t opcode) \ ((opcode >> (shift2)) & ((1 << (nb2)) - 1)); \ } -#define EXTRACT_HELPER_DXFORM(name, \ +#define EXTRACT_HELPER_SPLIT_3(name, \ d0_bits, shift_op_d0, shift_d0, \ d1_bits, shift_op_d1, shift_d1, \ d2_bits, shift_op_d2, shift_d2) \ @@ -156,7 +156,7 @@ EXTRACT_HELPER(FPFLM, 17, 8); EXTRACT_HELPER(FPW, 16, 1); /* addpcis */ -EXTRACT_HELPER_DXFORM(DX, 10, 6, 6, 5, 16, 1, 1, 0, 0) +EXTRACT_HELPER_SPLIT_3(DX, 10, 6, 6, 5, 16, 1, 1, 0, 0) #if defined(TARGET_PPC64) /* darn */ EXTRACT_HELPER(L, 16, 2); @@ -198,6 +198,7 @@ EXTRACT_HELPER(UIM, 16, 2); EXTRACT_HELPER(SHW, 8, 2); EXTRACT_HELPER(SP, 19, 2); EXTRACT_HELPER(IMM8, 11, 8); +EXTRACT_HELPER_SPLIT_3(DCMX_XV, 5, 16, 0, 1, 2, 5, 1, 6, 6); typedef union _ppc_vsr_t { uint8_t u8[16]; diff --git a/target/ppc/translate/vsx-impl.inc.c b/target/ppc/translate/vsx-impl.inc.c index 9bcc5af..adb6fc7 100644 --- a/target/ppc/translate/vsx-impl.inc.c +++ b/target/ppc/translate/vsx-impl.inc.c @@ -928,6 +928,8 @@ GEN_VSX_HELPER_2(xvrspic, 0x16, 0x0A, 0, PPC2_VSX) GEN_VSX_HELPER_2(xvrspim, 0x12, 0x0B, 0, PPC2_VSX) GEN_VSX_HELPER_2(xvrspip, 0x12, 0x0A, 0, PPC2_VSX) GEN_VSX_HELPER_2(xvrspiz, 0x12, 0x09, 0, PPC2_VSX) +GEN_VSX_HELPER_2(xvtstdcsp, 0x14, 0x1A, 0, PPC2_VSX) +GEN_VSX_HELPER_2(xvtstdcdp, 0x14, 0x1E, 0, PPC2_VSX) GEN_VSX_HELPER_2(xxperm, 0x08, 0x03, 0, PPC2_ISA300) GEN_VSX_HELPER_2(xxpermr, 0x08, 0x07, 0, PPC2_ISA300) diff --git a/target/ppc/translate/vsx-ops.inc.c b/target/ppc/translate/vsx-ops.inc.c index ee74312..6dd5d72 100644 --- a/target/ppc/translate/vsx-ops.inc.c +++ b/target/ppc/translate/vsx-ops.inc.c @@ -133,6 +133,14 @@ GEN_XX2FORM_EO(xvxsigdp, 0x16, 0x1D, 0x01, PPC2_ISA300), GEN_XX2FORM_EO(xvxexpsp, 0x16, 0x1D, 0x08, PPC2_ISA300), GEN_XX2FORM_EO(xvxsigsp, 0x16, 0x1D, 0x09, PPC2_ISA300), +/* DCMX = bit[25] << 6 | bit[29] << 5 | bit[11:15] */ +#define GEN_XX2FORM_DCMX(name, opc2, opc3, fl2) \ +GEN_XX3FORM(name, opc2, opc3 | 0, fl2), \ +GEN_XX3FORM(name, opc2, opc3 | 1, fl2) + +GEN_XX2FORM_DCMX(xvtstdcdp, 0x14, 0x1E, PPC2_ISA300), +GEN_XX2FORM_DCMX(xvtstdcsp, 0x14, 0x1A, PPC2_ISA300), + GEN_XX2FORM(xvabsdp, 0x12, 0x1D, PPC2_VSX), GEN_XX2FORM(xvnabsdp, 0x12, 0x1E, PPC2_VSX), GEN_XX2FORM(xvnegdp, 0x12, 0x1F, PPC2_VSX),