From patchwork Wed Dec 28 15:44:43 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Llu=C3=ADs_Vilanova?= X-Patchwork-Id: 709303 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3tpcZw1WKMz9sCG for ; Thu, 29 Dec 2016 02:48:24 +1100 (AEDT) Received: from localhost ([::1]:59740 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1cMGSk-00036G-40 for incoming@patchwork.ozlabs.org; Wed, 28 Dec 2016 10:48:22 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:38250) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1cMGQY-0001H4-8i for qemu-devel@nongnu.org; Wed, 28 Dec 2016 10:46:11 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1cMGQU-0004ys-2o for qemu-devel@nongnu.org; Wed, 28 Dec 2016 10:46:06 -0500 Received: from roura.ac.upc.es ([147.83.33.10]:60283) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1cMGQK-0004yH-2K; Wed, 28 Dec 2016 10:45:52 -0500 Received: from gw-2.ac.upc.es (gw-2.ac.upc.es [147.83.30.8]) by roura.ac.upc.es (8.13.8/8.13.8) with ESMTP id uBSFii0O010551; Wed, 28 Dec 2016 16:44:44 +0100 Received: from localhost (unknown [84.88.51.85]) by gw-2.ac.upc.es (Postfix) with ESMTPSA id 90C21A6; Wed, 28 Dec 2016 16:44:43 +0100 (CET) From: =?utf-8?b?TGx1w61z?= Vilanova To: qemu-devel@nongnu.org Date: Wed, 28 Dec 2016 16:44:43 +0100 Message-Id: <148293988310.31645.17310296111845545049.stgit@fimbulvetr.bsc.es> X-Mailer: git-send-email 2.11.0 In-Reply-To: <148293987753.31645.8166717498506500137.stgit@fimbulvetr.bsc.es> References: <148293987753.31645.8166717498506500137.stgit@fimbulvetr.bsc.es> User-Agent: StGit/0.17.1-dirty MIME-Version: 1.0 X-MIME-Autoconverted: from 8bit to quoted-printable by roura.ac.upc.es id uBSFii0O010551 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.6.x [fuzzy] X-Received-From: 147.83.33.10 Subject: [Qemu-devel] [PATCH v4 1/6] Pass generic CPUState to gen_intermediate_code() X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , Guan Xuetao , Eduardo Habkost , Peter Crosthwaite , Jia Liu , Anthony Green , Mark Cave-Ayland , Laurent Vivier , Bastian Koppelmann , Alexander Graf , Max Filippov , Michael Walle , "open list:ARM" , "open list:PowerPC" , Artyom Tarasenko , "Edgar E. Iglesias" , Yongbok Kim , Paolo Bonzini , David Gibson , Aurelien Jarno , Richard Henderson Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Needed to implement a target-agnostic gen_intermediate_code() in the future. Signed-off-by: Lluís Vilanova Reviewed-by: David Gibson --- include/exec/exec-all.h | 2 +- target-alpha/translate.c | 11 +++++------ target-arm/translate.c | 24 ++++++++++++------------ target-cris/translate.c | 17 ++++++++--------- target-i386/translate.c | 13 ++++++------- target-lm32/translate.c | 22 +++++++++++----------- target-m68k/translate.c | 15 +++++++-------- target-microblaze/translate.c | 22 +++++++++++----------- target-mips/translate.c | 15 +++++++-------- target-moxie/translate.c | 14 +++++++------- target-openrisc/translate.c | 22 +++++++++++----------- target-ppc/translate.c | 15 +++++++-------- target-s390x/translate.c | 13 ++++++------- target-sh4/translate.c | 15 +++++++-------- target-sparc/translate.c | 11 +++++------ target-tilegx/translate.c | 7 +++---- target-tricore/translate.c | 9 ++++----- target-unicore32/translate.c | 17 ++++++++--------- target-xtensa/translate.c | 13 ++++++------- translate-all.c | 2 +- 20 files changed, 133 insertions(+), 146 deletions(-) diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h index a8c13cee66..0e45e1aedc 100644 --- a/include/exec/exec-all.h +++ b/include/exec/exec-all.h @@ -43,7 +43,7 @@ typedef ram_addr_t tb_page_addr_t; #include "qemu/log.h" -void gen_intermediate_code(CPUArchState *env, struct TranslationBlock *tb); +void gen_intermediate_code(CPUState *env, struct TranslationBlock *tb); void restore_state_to_opc(CPUArchState *env, struct TranslationBlock *tb, target_ulong *data); diff --git a/target-alpha/translate.c b/target-alpha/translate.c index 114927b751..6759ec28cc 100644 --- a/target-alpha/translate.c +++ b/target-alpha/translate.c @@ -2873,10 +2873,9 @@ static ExitStatus translate_one(DisasContext *ctx, uint32_t insn) return ret; } -void gen_intermediate_code(CPUAlphaState *env, struct TranslationBlock *tb) +void gen_intermediate_code(CPUState *cpu, struct TranslationBlock *tb) { - AlphaCPU *cpu = alpha_env_get_cpu(env); - CPUState *cs = CPU(cpu); + CPUAlphaState *env = cpu->env_ptr; DisasContext ctx, *ctxp = &ctx; target_ulong pc_start; target_ulong pc_mask; @@ -2891,7 +2890,7 @@ void gen_intermediate_code(CPUAlphaState *env, struct TranslationBlock *tb) ctx.pc = pc_start; ctx.mem_idx = cpu_mmu_index(env, false); ctx.implver = env->implver; - ctx.singlestep_enabled = cs->singlestep_enabled; + ctx.singlestep_enabled = cpu->singlestep_enabled; #ifdef CONFIG_USER_ONLY ctx.ir = cpu_std_ir; @@ -2934,7 +2933,7 @@ void gen_intermediate_code(CPUAlphaState *env, struct TranslationBlock *tb) tcg_gen_insn_start(ctx.pc); num_insns++; - if (unlikely(cpu_breakpoint_test(cs, ctx.pc, BP_ANY))) { + if (unlikely(cpu_breakpoint_test(cpu, ctx.pc, BP_ANY))) { ret = gen_excp(&ctx, EXCP_DEBUG, 0); /* The address covered by the breakpoint must be included in [tb->pc, tb->pc + tb->size) in order to for it to be @@ -2996,7 +2995,7 @@ void gen_intermediate_code(CPUAlphaState *env, struct TranslationBlock *tb) && qemu_log_in_addr_range(pc_start)) { qemu_log_lock(); qemu_log("IN: %s\n", lookup_symbol(pc_start)); - log_target_disas(cs, pc_start, ctx.pc - pc_start, 1); + log_target_disas(cpu, pc_start, ctx.pc - pc_start, 1); qemu_log("\n"); qemu_log_unlock(); } diff --git a/target-arm/translate.c b/target-arm/translate.c index 0ad9070b45..3aa766901c 100644 --- a/target-arm/translate.c +++ b/target-arm/translate.c @@ -11589,10 +11589,10 @@ static bool insn_crosses_page(CPUARMState *env, DisasContext *s) } /* generate intermediate code for basic block 'tb'. */ -void gen_intermediate_code(CPUARMState *env, TranslationBlock *tb) +void gen_intermediate_code(CPUState *cpu, TranslationBlock *tb) { - ARMCPU *cpu = arm_env_get_cpu(env); - CPUState *cs = CPU(cpu); + CPUARMState *env = cpu->env_ptr; + ARMCPU *arm_cpu = arm_env_get_cpu(env); DisasContext dc1, *dc = &dc1; target_ulong pc_start; target_ulong next_page_start; @@ -11606,7 +11606,7 @@ void gen_intermediate_code(CPUARMState *env, TranslationBlock *tb) * the A32/T32 complexity to do with conditional execution/IT blocks/etc. */ if (ARM_TBFLAG_AARCH64_STATE(tb->flags)) { - gen_intermediate_code_a64(cpu, tb); + gen_intermediate_code_a64(arm_cpu, tb); return; } @@ -11616,7 +11616,7 @@ void gen_intermediate_code(CPUARMState *env, TranslationBlock *tb) dc->is_jmp = DISAS_NEXT; dc->pc = pc_start; - dc->singlestep_enabled = cs->singlestep_enabled; + dc->singlestep_enabled = cpu->singlestep_enabled; dc->condjmp = 0; dc->aarch64 = 0; @@ -11641,7 +11641,7 @@ void gen_intermediate_code(CPUARMState *env, TranslationBlock *tb) dc->vec_len = ARM_TBFLAG_VECLEN(tb->flags); dc->vec_stride = ARM_TBFLAG_VECSTRIDE(tb->flags); dc->c15_cpar = ARM_TBFLAG_XSCALE_CPAR(tb->flags); - dc->cp_regs = cpu->cp_regs; + dc->cp_regs = arm_cpu->cp_regs; dc->features = env->features; /* Single step state. The code-generation logic here is: @@ -11749,9 +11749,9 @@ void gen_intermediate_code(CPUARMState *env, TranslationBlock *tb) } #endif - if (unlikely(!QTAILQ_EMPTY(&cs->breakpoints))) { + if (unlikely(!QTAILQ_EMPTY(&cpu->breakpoints))) { CPUBreakpoint *bp; - QTAILQ_FOREACH(bp, &cs->breakpoints, entry) { + QTAILQ_FOREACH(bp, &cpu->breakpoints, entry) { if (bp->pc == dc->pc) { if (bp->flags & BP_CPU) { gen_set_condexec(dc); @@ -11841,7 +11841,7 @@ void gen_intermediate_code(CPUARMState *env, TranslationBlock *tb) ((dc->pc >= next_page_start - 3) && insn_crosses_page(env, dc)); } while (!dc->is_jmp && !tcg_op_buf_full() && - !cs->singlestep_enabled && + !cpu->singlestep_enabled && !singlestep && !dc->ss_active && !end_of_page && @@ -11851,7 +11851,7 @@ void gen_intermediate_code(CPUARMState *env, TranslationBlock *tb) if (dc->condjmp) { /* FIXME: This can theoretically happen with self-modifying code. */ - cpu_abort(cs, "IO on conditional branch instruction"); + cpu_abort(cpu, "IO on conditional branch instruction"); } gen_io_end(); } @@ -11859,7 +11859,7 @@ void gen_intermediate_code(CPUARMState *env, TranslationBlock *tb) /* At this stage dc->condjmp will only be set when the skipped instruction was a conditional branch or trap, and the PC has already been written. */ - if (unlikely(cs->singlestep_enabled || dc->ss_active)) { + if (unlikely(cpu->singlestep_enabled || dc->ss_active)) { /* Unconditional and "condition passed" instruction codepath. */ gen_set_condexec(dc); switch (dc->is_jmp) { @@ -11966,7 +11966,7 @@ done_generating: qemu_log_lock(); qemu_log("----------------\n"); qemu_log("IN: %s\n", lookup_symbol(pc_start)); - log_target_disas(cs, pc_start, dc->pc - pc_start, + log_target_disas(cpu, pc_start, dc->pc - pc_start, dc->thumb | (dc->sctlr_b << 1)); qemu_log("\n"); qemu_log_unlock(); diff --git a/target-cris/translate.c b/target-cris/translate.c index b91042743f..ebcf7863bf 100644 --- a/target-cris/translate.c +++ b/target-cris/translate.c @@ -3080,10 +3080,9 @@ static unsigned int crisv32_decoder(CPUCRISState *env, DisasContext *dc) */ /* generate intermediate code for basic block 'tb'. */ -void gen_intermediate_code(CPUCRISState *env, struct TranslationBlock *tb) +void gen_intermediate_code(CPUState *cpu, struct TranslationBlock *tb) { - CRISCPU *cpu = cris_env_get_cpu(env); - CPUState *cs = CPU(cpu); + CPUCRISState *env = cpu->env_ptr; uint32_t pc_start; unsigned int insn_len; struct DisasContext ctx; @@ -3105,13 +3104,13 @@ void gen_intermediate_code(CPUCRISState *env, struct TranslationBlock *tb) * delayslot, like in real hw. */ pc_start = tb->pc & ~1; - dc->cpu = cpu; + dc->cpu = cris_env_get_cpu(env); dc->tb = tb; dc->is_jmp = DISAS_NEXT; dc->ppc = pc_start; dc->pc = pc_start; - dc->singlestep_enabled = cs->singlestep_enabled; + dc->singlestep_enabled = cpu->singlestep_enabled; dc->flags_uptodate = 1; dc->flagx_known = 1; dc->flags_x = tb->flags & X_FLAG; @@ -3151,7 +3150,7 @@ void gen_intermediate_code(CPUCRISState *env, struct TranslationBlock *tb) ? dc->ppc | 1 : dc->pc); num_insns++; - if (unlikely(cpu_breakpoint_test(cs, dc->pc, BP_ANY))) { + if (unlikely(cpu_breakpoint_test(cpu, dc->pc, BP_ANY))) { cris_evaluate_flags(dc); tcg_gen_movi_tl(env_pc, dc->pc); t_gen_raise_exception(EXCP_DEBUG); @@ -3225,7 +3224,7 @@ void gen_intermediate_code(CPUCRISState *env, struct TranslationBlock *tb) /* If we are rexecuting a branch due to exceptions on delay slots don't break. */ - if (!(tb->pc & 1) && cs->singlestep_enabled) { + if (!(tb->pc & 1) && cpu->singlestep_enabled) { break; } } while (!dc->is_jmp && !dc->cpustate_changed @@ -3258,7 +3257,7 @@ void gen_intermediate_code(CPUCRISState *env, struct TranslationBlock *tb) cris_evaluate_flags(dc); - if (unlikely(cs->singlestep_enabled)) { + if (unlikely(cpu->singlestep_enabled)) { if (dc->is_jmp == DISAS_NEXT) { tcg_gen_movi_tl(env_pc, npc); } @@ -3293,7 +3292,7 @@ void gen_intermediate_code(CPUCRISState *env, struct TranslationBlock *tb) qemu_log_lock(); qemu_log("--------------\n"); qemu_log("IN: %s\n", lookup_symbol(pc_start)); - log_target_disas(cs, pc_start, dc->pc - pc_start, + log_target_disas(cpu, pc_start, dc->pc - pc_start, env->pregs[PR_VR]); qemu_log("\nisize=%d osize=%d\n", dc->pc - pc_start, tcg_op_buf_count()); diff --git a/target-i386/translate.c b/target-i386/translate.c index 324103c885..61d73e286f 100644 --- a/target-i386/translate.c +++ b/target-i386/translate.c @@ -8308,10 +8308,9 @@ void tcg_x86_init(void) } /* generate intermediate code for basic block 'tb'. */ -void gen_intermediate_code(CPUX86State *env, TranslationBlock *tb) +void gen_intermediate_code(CPUState *cpu, TranslationBlock *tb) { - X86CPU *cpu = x86_env_get_cpu(env); - CPUState *cs = CPU(cpu); + CPUX86State *env = cpu->env_ptr; DisasContext dc1, *dc = &dc1; target_ulong pc_ptr; uint32_t flags; @@ -8334,7 +8333,7 @@ void gen_intermediate_code(CPUX86State *env, TranslationBlock *tb) dc->cpl = (flags >> HF_CPL_SHIFT) & 3; dc->iopl = (flags >> IOPL_SHIFT) & 3; dc->tf = (flags >> TF_SHIFT) & 1; - dc->singlestep_enabled = cs->singlestep_enabled; + dc->singlestep_enabled = cpu->singlestep_enabled; dc->cc_op = CC_OP_DYNAMIC; dc->cc_op_dirty = false; dc->cs_base = cs_base; @@ -8356,7 +8355,7 @@ void gen_intermediate_code(CPUX86State *env, TranslationBlock *tb) dc->code64 = (flags >> HF_CS64_SHIFT) & 1; #endif dc->flags = flags; - dc->jmp_opt = !(dc->tf || cs->singlestep_enabled || + dc->jmp_opt = !(dc->tf || cpu->singlestep_enabled || (flags & HF_INHIBIT_IRQ_MASK)); /* Do not optimize repz jumps at all in icount mode, because rep movsS instructions are execured with different paths @@ -8405,7 +8404,7 @@ void gen_intermediate_code(CPUX86State *env, TranslationBlock *tb) num_insns++; /* If RF is set, suppress an internally generated breakpoint. */ - if (unlikely(cpu_breakpoint_test(cs, pc_ptr, + if (unlikely(cpu_breakpoint_test(cpu, pc_ptr, tb->flags & HF_RF_MASK ? BP_GDB : BP_ANY))) { gen_debug(dc, pc_ptr - dc->cs_base); @@ -8481,7 +8480,7 @@ done_generating: else #endif disas_flags = !dc->code32; - log_target_disas(cs, pc_start, pc_ptr - pc_start, disas_flags); + log_target_disas(cpu, pc_start, pc_ptr - pc_start, disas_flags); qemu_log("\n"); qemu_log_unlock(); } diff --git a/target-lm32/translate.c b/target-lm32/translate.c index 692882f447..0ac34fc620 100644 --- a/target-lm32/translate.c +++ b/target-lm32/translate.c @@ -1044,10 +1044,10 @@ static inline void decode(DisasContext *dc, uint32_t ir) } /* generate intermediate code for basic block 'tb'. */ -void gen_intermediate_code(CPULM32State *env, struct TranslationBlock *tb) +void gen_intermediate_code(CPUState *cpu, struct TranslationBlock *tb) { - LM32CPU *cpu = lm32_env_get_cpu(env); - CPUState *cs = CPU(cpu); + CPULM32State *env = cpu->env_ptr; + LM32CPU *lm32_cpu = lm32_env_get_cpu(env); struct DisasContext ctx, *dc = &ctx; uint32_t pc_start; uint32_t next_page_start; @@ -1055,14 +1055,14 @@ void gen_intermediate_code(CPULM32State *env, struct TranslationBlock *tb) int max_insns; pc_start = tb->pc; - dc->features = cpu->features; - dc->num_breakpoints = cpu->num_breakpoints; - dc->num_watchpoints = cpu->num_watchpoints; + dc->features = lm32_cpu->features; + dc->num_breakpoints = lm32_cpu->num_breakpoints; + dc->num_watchpoints = lm32_cpu->num_watchpoints; dc->tb = tb; dc->is_jmp = DISAS_NEXT; dc->pc = pc_start; - dc->singlestep_enabled = cs->singlestep_enabled; + dc->singlestep_enabled = cpu->singlestep_enabled; if (pc_start & 3) { qemu_log_mask(LOG_GUEST_ERROR, @@ -1085,7 +1085,7 @@ void gen_intermediate_code(CPULM32State *env, struct TranslationBlock *tb) tcg_gen_insn_start(dc->pc); num_insns++; - if (unlikely(cpu_breakpoint_test(cs, dc->pc, BP_ANY))) { + if (unlikely(cpu_breakpoint_test(cpu, dc->pc, BP_ANY))) { tcg_gen_movi_tl(cpu_pc, dc->pc); t_gen_raise_exception(dc, EXCP_DEBUG); dc->is_jmp = DISAS_UPDATE; @@ -1108,7 +1108,7 @@ void gen_intermediate_code(CPULM32State *env, struct TranslationBlock *tb) dc->pc += 4; } while (!dc->is_jmp && !tcg_op_buf_full() - && !cs->singlestep_enabled + && !cpu->singlestep_enabled && !singlestep && (dc->pc < next_page_start) && num_insns < max_insns); @@ -1117,7 +1117,7 @@ void gen_intermediate_code(CPULM32State *env, struct TranslationBlock *tb) gen_io_end(); } - if (unlikely(cs->singlestep_enabled)) { + if (unlikely(cpu->singlestep_enabled)) { if (dc->is_jmp == DISAS_NEXT) { tcg_gen_movi_tl(cpu_pc, dc->pc); } @@ -1150,7 +1150,7 @@ void gen_intermediate_code(CPULM32State *env, struct TranslationBlock *tb) && qemu_log_in_addr_range(pc_start)) { qemu_log_lock(); qemu_log("\n"); - log_target_disas(cs, pc_start, dc->pc - pc_start, 0); + log_target_disas(cpu, pc_start, dc->pc - pc_start, 0); qemu_log("\nisize=%d osize=%d\n", dc->pc - pc_start, tcg_op_buf_count()); qemu_log_unlock(); diff --git a/target-m68k/translate.c b/target-m68k/translate.c index d6ed883882..6da6f2b51b 100644 --- a/target-m68k/translate.c +++ b/target-m68k/translate.c @@ -3454,10 +3454,9 @@ static void disas_m68k_insn(CPUM68KState * env, DisasContext *s) } /* generate intermediate code for basic block 'tb'. */ -void gen_intermediate_code(CPUM68KState *env, TranslationBlock *tb) +void gen_intermediate_code(CPUState *cpu, TranslationBlock *tb) { - M68kCPU *cpu = m68k_env_get_cpu(env); - CPUState *cs = CPU(cpu); + CPUM68KState *env = cpu->env_ptr; DisasContext dc1, *dc = &dc1; target_ulong pc_start; int pc_offset; @@ -3474,7 +3473,7 @@ void gen_intermediate_code(CPUM68KState *env, TranslationBlock *tb) dc->pc = pc_start; dc->cc_op = CC_OP_DYNAMIC; dc->cc_op_synced = 1; - dc->singlestep_enabled = cs->singlestep_enabled; + dc->singlestep_enabled = cpu->singlestep_enabled; dc->fpcr = env->fpcr; dc->user = (env->sr & SR_S) == 0; dc->done_mac = 0; @@ -3494,7 +3493,7 @@ void gen_intermediate_code(CPUM68KState *env, TranslationBlock *tb) tcg_gen_insn_start(dc->pc, dc->cc_op); num_insns++; - if (unlikely(cpu_breakpoint_test(cs, dc->pc, BP_ANY))) { + if (unlikely(cpu_breakpoint_test(cpu, dc->pc, BP_ANY))) { gen_exception(dc, dc->pc, EXCP_DEBUG); dc->is_jmp = DISAS_JUMP; /* The address covered by the breakpoint must be included in @@ -3512,14 +3511,14 @@ void gen_intermediate_code(CPUM68KState *env, TranslationBlock *tb) dc->insn_pc = dc->pc; disas_m68k_insn(env, dc); } while (!dc->is_jmp && !tcg_op_buf_full() && - !cs->singlestep_enabled && + !cpu->singlestep_enabled && !singlestep && (pc_offset) < (TARGET_PAGE_SIZE - 32) && num_insns < max_insns); if (tb->cflags & CF_LAST_IO) gen_io_end(); - if (unlikely(cs->singlestep_enabled)) { + if (unlikely(cpu->singlestep_enabled)) { /* Make sure the pc is updated, and raise a debug exception. */ if (!dc->is_jmp) { update_cc_op(dc); @@ -3552,7 +3551,7 @@ void gen_intermediate_code(CPUM68KState *env, TranslationBlock *tb) qemu_log_lock(); qemu_log("----------------\n"); qemu_log("IN: %s\n", lookup_symbol(pc_start)); - log_target_disas(cs, pc_start, dc->pc - pc_start, 0); + log_target_disas(cpu, pc_start, dc->pc - pc_start, 0); qemu_log("\n"); qemu_log_unlock(); } diff --git a/target-microblaze/translate.c b/target-microblaze/translate.c index de2090ac71..5289718643 100644 --- a/target-microblaze/translate.c +++ b/target-microblaze/translate.c @@ -1594,10 +1594,10 @@ static inline void decode(DisasContext *dc, uint32_t ir) } /* generate intermediate code for basic block 'tb'. */ -void gen_intermediate_code(CPUMBState *env, struct TranslationBlock *tb) +void gen_intermediate_code(CPUState *cpu, struct TranslationBlock *tb) { - MicroBlazeCPU *cpu = mb_env_get_cpu(env); - CPUState *cs = CPU(cpu); + CPUMBState *env = cpu->env_ptr; + MicroBlazeCPU *mb_cpu = mb_env_get_cpu(env); uint32_t pc_start; struct DisasContext ctx; struct DisasContext *dc = &ctx; @@ -1607,7 +1607,7 @@ void gen_intermediate_code(CPUMBState *env, struct TranslationBlock *tb) int max_insns; pc_start = tb->pc; - dc->cpu = cpu; + dc->cpu = mb_cpu; dc->tb = tb; org_flags = dc->synced_flags = dc->tb_flags = tb->flags; @@ -1618,13 +1618,13 @@ void gen_intermediate_code(CPUMBState *env, struct TranslationBlock *tb) dc->jmp = JMP_INDIRECT; } dc->pc = pc_start; - dc->singlestep_enabled = cs->singlestep_enabled; + dc->singlestep_enabled = cpu->singlestep_enabled; dc->cpustate_changed = 0; dc->abort_at_next_insn = 0; dc->nr_nops = 0; if (pc_start & 3) { - cpu_abort(cs, "Microblaze: unaligned PC=%x\n", pc_start); + cpu_abort(cpu, "Microblaze: unaligned PC=%x\n", pc_start); } next_page_start = (pc_start & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE; @@ -1650,7 +1650,7 @@ void gen_intermediate_code(CPUMBState *env, struct TranslationBlock *tb) } #endif - if (unlikely(cpu_breakpoint_test(cs, dc->pc, BP_ANY))) { + if (unlikely(cpu_breakpoint_test(cpu, dc->pc, BP_ANY))) { t_gen_raise_exception(dc, EXCP_DEBUG); dc->is_jmp = DISAS_UPDATE; /* The address covered by the breakpoint must be included in @@ -1707,7 +1707,7 @@ void gen_intermediate_code(CPUMBState *env, struct TranslationBlock *tb) break; } } - if (cs->singlestep_enabled) { + if (cpu->singlestep_enabled) { break; } } while (!dc->is_jmp && !dc->cpustate_changed @@ -1728,7 +1728,7 @@ void gen_intermediate_code(CPUMBState *env, struct TranslationBlock *tb) if (tb->cflags & CF_LAST_IO) gen_io_end(); - /* Force an update if the per-tb cpu state has changed. */ + /* Force an update if the per-tb mb_cpu state has changed. */ if (dc->is_jmp == DISAS_NEXT && (dc->cpustate_changed || org_flags != dc->tb_flags)) { dc->is_jmp = DISAS_UPDATE; @@ -1736,7 +1736,7 @@ void gen_intermediate_code(CPUMBState *env, struct TranslationBlock *tb) } t_sync_flags(dc); - if (unlikely(cs->singlestep_enabled)) { + if (unlikely(cpu->singlestep_enabled)) { TCGv_i32 tmp = tcg_const_i32(EXCP_DEBUG); if (dc->is_jmp != DISAS_JUMP) { @@ -1773,7 +1773,7 @@ void gen_intermediate_code(CPUMBState *env, struct TranslationBlock *tb) qemu_log_lock(); qemu_log("--------------\n"); #if DISAS_GNU - log_target_disas(cs, pc_start, dc->pc - pc_start, 0); + log_target_disas(cpu, pc_start, dc->pc - pc_start, 0); #endif qemu_log("\nisize=%d osize=%d\n", dc->pc - pc_start, tcg_op_buf_count()); diff --git a/target-mips/translate.c b/target-mips/translate.c index 57b824ff2d..7441ef5446 100644 --- a/target-mips/translate.c +++ b/target-mips/translate.c @@ -19878,10 +19878,9 @@ static void decode_opc(CPUMIPSState *env, DisasContext *ctx) } } -void gen_intermediate_code(CPUMIPSState *env, struct TranslationBlock *tb) +void gen_intermediate_code(CPUState *cpu, struct TranslationBlock *tb) { - MIPSCPU *cpu = mips_env_get_cpu(env); - CPUState *cs = CPU(cpu); + CPUMIPSState *env = cpu->env_ptr; DisasContext ctx; target_ulong pc_start; target_ulong next_page_start; @@ -19894,7 +19893,7 @@ void gen_intermediate_code(CPUMIPSState *env, struct TranslationBlock *tb) next_page_start = (pc_start & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE; ctx.pc = pc_start; ctx.saved_pc = -1; - ctx.singlestep_enabled = cs->singlestep_enabled; + ctx.singlestep_enabled = cpu->singlestep_enabled; ctx.insn_flags = env->insn_flags; ctx.CP0_Config1 = env->CP0_Config1; ctx.tb = tb; @@ -19941,7 +19940,7 @@ void gen_intermediate_code(CPUMIPSState *env, struct TranslationBlock *tb) tcg_gen_insn_start(ctx.pc, ctx.hflags & MIPS_HFLAG_BMASK, ctx.btarget); num_insns++; - if (unlikely(cpu_breakpoint_test(cs, ctx.pc, BP_ANY))) { + if (unlikely(cpu_breakpoint_test(cpu, ctx.pc, BP_ANY))) { save_cpu_state(&ctx, 1); ctx.bstate = BS_BRANCH; gen_helper_raise_exception_debug(cpu_env); @@ -19996,7 +19995,7 @@ void gen_intermediate_code(CPUMIPSState *env, struct TranslationBlock *tb) This is what GDB expects and is consistent with what the hardware does (e.g. if a delay slot instruction faults, the reported PC is the PC of the branch). */ - if (cs->singlestep_enabled && (ctx.hflags & MIPS_HFLAG_BMASK) == 0) { + if (cpu->singlestep_enabled && (ctx.hflags & MIPS_HFLAG_BMASK) == 0) { break; } @@ -20017,7 +20016,7 @@ void gen_intermediate_code(CPUMIPSState *env, struct TranslationBlock *tb) if (tb->cflags & CF_LAST_IO) { gen_io_end(); } - if (cs->singlestep_enabled && ctx.bstate != BS_BRANCH) { + if (cpu->singlestep_enabled && ctx.bstate != BS_BRANCH) { save_cpu_state(&ctx, ctx.bstate != BS_EXCP); gen_helper_raise_exception_debug(cpu_env); } else { @@ -20049,7 +20048,7 @@ done_generating: && qemu_log_in_addr_range(pc_start)) { qemu_log_lock(); qemu_log("IN: %s\n", lookup_symbol(pc_start)); - log_target_disas(cs, pc_start, ctx.pc - pc_start, 0); + log_target_disas(cpu, pc_start, ctx.pc - pc_start, 0); qemu_log("\n"); qemu_log_unlock(); } diff --git a/target-moxie/translate.c b/target-moxie/translate.c index 0660b44c08..176063a1de 100644 --- a/target-moxie/translate.c +++ b/target-moxie/translate.c @@ -822,10 +822,10 @@ static int decode_opc(MoxieCPU *cpu, DisasContext *ctx) } /* generate intermediate code for basic block 'tb'. */ -void gen_intermediate_code(CPUMoxieState *env, struct TranslationBlock *tb) +void gen_intermediate_code(CPUState *cpu, struct TranslationBlock *tb) { - MoxieCPU *cpu = moxie_env_get_cpu(env); - CPUState *cs = CPU(cpu); + CPUMoxieState *env = cpu->env_ptr; + MoxieCPU *moxie_cpu = moxie_env_get_cpu(env); DisasContext ctx; target_ulong pc_start; int num_insns, max_insns; @@ -851,7 +851,7 @@ void gen_intermediate_code(CPUMoxieState *env, struct TranslationBlock *tb) tcg_gen_insn_start(ctx.pc); num_insns++; - if (unlikely(cpu_breakpoint_test(cs, ctx.pc, BP_ANY))) { + if (unlikely(cpu_breakpoint_test(cpu, ctx.pc, BP_ANY))) { tcg_gen_movi_i32(cpu_pc, ctx.pc); gen_helper_debug(cpu_env); ctx.bstate = BS_EXCP; @@ -864,12 +864,12 @@ void gen_intermediate_code(CPUMoxieState *env, struct TranslationBlock *tb) } ctx.opcode = cpu_lduw_code(env, ctx.pc); - ctx.pc += decode_opc(cpu, &ctx); + ctx.pc += decode_opc(moxie_cpu, &ctx); if (num_insns >= max_insns) { break; } - if (cs->singlestep_enabled) { + if (cpu->singlestep_enabled) { break; } if ((ctx.pc & (TARGET_PAGE_SIZE - 1)) == 0) { @@ -877,7 +877,7 @@ void gen_intermediate_code(CPUMoxieState *env, struct TranslationBlock *tb) } } while (ctx.bstate == BS_NONE && !tcg_op_buf_full()); - if (cs->singlestep_enabled) { + if (cpu->singlestep_enabled) { tcg_gen_movi_tl(cpu_pc, ctx.pc); gen_helper_debug(cpu_env); } else { diff --git a/target-openrisc/translate.c b/target-openrisc/translate.c index 229361aed1..a509234500 100644 --- a/target-openrisc/translate.c +++ b/target-openrisc/translate.c @@ -1630,10 +1630,10 @@ static void disas_openrisc_insn(DisasContext *dc, OpenRISCCPU *cpu) } } -void gen_intermediate_code(CPUOpenRISCState *env, struct TranslationBlock *tb) +void gen_intermediate_code(CPUState *cpu, struct TranslationBlock *tb) { - OpenRISCCPU *cpu = openrisc_env_get_cpu(env); - CPUState *cs = CPU(cpu); + CPUOpenRISCState *env = cpu->env_ptr; + OpenRISCCPU *or_cpu = openrisc_env_get_cpu(env); struct DisasContext ctx, *dc = &ctx; uint32_t pc_start; uint32_t next_page_start; @@ -1646,11 +1646,11 @@ void gen_intermediate_code(CPUOpenRISCState *env, struct TranslationBlock *tb) dc->is_jmp = DISAS_NEXT; dc->ppc = pc_start; dc->pc = pc_start; - dc->flags = cpu->env.cpucfgr; - dc->mem_idx = cpu_mmu_index(&cpu->env, false); + dc->flags = or_cpu->env.cpucfgr; + dc->mem_idx = cpu_mmu_index(&or_cpu->env, false); dc->synced_flags = dc->tb_flags = tb->flags; dc->delayed_branch = !!(dc->tb_flags & D_FLAG); - dc->singlestep_enabled = cs->singlestep_enabled; + dc->singlestep_enabled = cpu->singlestep_enabled; next_page_start = (pc_start & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE; num_insns = 0; @@ -1669,7 +1669,7 @@ void gen_intermediate_code(CPUOpenRISCState *env, struct TranslationBlock *tb) tcg_gen_insn_start(dc->pc); num_insns++; - if (unlikely(cpu_breakpoint_test(cs, dc->pc, BP_ANY))) { + if (unlikely(cpu_breakpoint_test(cpu, dc->pc, BP_ANY))) { tcg_gen_movi_tl(cpu_pc, dc->pc); gen_exception(dc, EXCP_DEBUG); dc->is_jmp = DISAS_UPDATE; @@ -1688,7 +1688,7 @@ void gen_intermediate_code(CPUOpenRISCState *env, struct TranslationBlock *tb) dc->npc = dc->pc + 4; tcg_gen_movi_tl(cpu_ppc, dc->ppc); tcg_gen_movi_tl(cpu_npc, dc->npc); - disas_openrisc_insn(dc, cpu); + disas_openrisc_insn(dc, or_cpu); dc->pc = dc->npc; /* delay slot */ if (dc->delayed_branch) { @@ -1706,7 +1706,7 @@ void gen_intermediate_code(CPUOpenRISCState *env, struct TranslationBlock *tb) } } while (!dc->is_jmp && !tcg_op_buf_full() - && !cs->singlestep_enabled + && !cpu->singlestep_enabled && !singlestep && (dc->pc < next_page_start) && num_insns < max_insns); @@ -1718,7 +1718,7 @@ void gen_intermediate_code(CPUOpenRISCState *env, struct TranslationBlock *tb) dc->is_jmp = DISAS_UPDATE; tcg_gen_movi_tl(cpu_pc, dc->pc); } - if (unlikely(cs->singlestep_enabled)) { + if (unlikely(cpu->singlestep_enabled)) { if (dc->is_jmp == DISAS_NEXT) { tcg_gen_movi_tl(cpu_pc, dc->pc); } @@ -1753,7 +1753,7 @@ void gen_intermediate_code(CPUOpenRISCState *env, struct TranslationBlock *tb) qemu_log_lock(); qemu_log("----------------\n"); qemu_log("IN: %s\n", lookup_symbol(pc_start)); - log_target_disas(cs, pc_start, dc->pc - pc_start, 0); + log_target_disas(cpu, pc_start, dc->pc - pc_start, 0); qemu_log("\nisize=%d osize=%d\n", dc->pc - pc_start, tcg_op_buf_count()); qemu_log_unlock(); diff --git a/target-ppc/translate.c b/target-ppc/translate.c index 59e9552d2b..d7c35084df 100644 --- a/target-ppc/translate.c +++ b/target-ppc/translate.c @@ -6982,10 +6982,9 @@ void ppc_cpu_dump_statistics(CPUState *cs, FILE*f, } /*****************************************************************************/ -void gen_intermediate_code(CPUPPCState *env, struct TranslationBlock *tb) +void gen_intermediate_code(CPUState *cpu, struct TranslationBlock *tb) { - PowerPCCPU *cpu = ppc_env_get_cpu(env); - CPUState *cs = CPU(cpu); + CPUPPCState *env = cpu->env_ptr; DisasContext ctx, *ctxp = &ctx; opc_handler_t **table, *handler; target_ulong pc_start; @@ -7045,7 +7044,7 @@ void gen_intermediate_code(CPUPPCState *env, struct TranslationBlock *tb) ctx.singlestep_enabled = 0; if ((env->flags & POWERPC_FLAG_BE) && msr_be) ctx.singlestep_enabled |= CPU_BRANCH_STEP; - if (unlikely(cs->singlestep_enabled)) { + if (unlikely(cpu->singlestep_enabled)) { ctx.singlestep_enabled |= GDBSTUB_SINGLE_STEP; } #if defined (DO_SINGLE_STEP) && 0 @@ -7068,7 +7067,7 @@ void gen_intermediate_code(CPUPPCState *env, struct TranslationBlock *tb) tcg_gen_insn_start(ctx.nip); num_insns++; - if (unlikely(cpu_breakpoint_test(cs, ctx.nip, BP_ANY))) { + if (unlikely(cpu_breakpoint_test(cpu, ctx.nip, BP_ANY))) { gen_debug_exception(ctxp); /* The address covered by the breakpoint must be included in [tb->pc, tb->pc + tb->size) in order to for it to be @@ -7147,7 +7146,7 @@ void gen_intermediate_code(CPUPPCState *env, struct TranslationBlock *tb) ctx.exception != POWERPC_EXCP_BRANCH)) { gen_exception_nip(ctxp, POWERPC_EXCP_TRACE, ctx.nip); } else if (unlikely(((ctx.nip & (TARGET_PAGE_SIZE - 1)) == 0) || - (cs->singlestep_enabled) || + (cpu->singlestep_enabled) || singlestep || num_insns >= max_insns)) { /* if we reach a page boundary or are single stepping, stop @@ -7167,7 +7166,7 @@ void gen_intermediate_code(CPUPPCState *env, struct TranslationBlock *tb) if (ctx.exception == POWERPC_EXCP_NONE) { gen_goto_tb(&ctx, 0, ctx.nip); } else if (ctx.exception != POWERPC_EXCP_BRANCH) { - if (unlikely(cs->singlestep_enabled)) { + if (unlikely(cpu->singlestep_enabled)) { gen_debug_exception(ctxp); } /* Generate the return instruction */ @@ -7186,7 +7185,7 @@ void gen_intermediate_code(CPUPPCState *env, struct TranslationBlock *tb) flags |= ctx.le_mode << 16; qemu_log_lock(); qemu_log("IN: %s\n", lookup_symbol(pc_start)); - log_target_disas(cs, pc_start, ctx.nip - pc_start, flags); + log_target_disas(cpu, pc_start, ctx.nip - pc_start, flags); qemu_log("\n"); qemu_log_unlock(); } diff --git a/target-s390x/translate.c b/target-s390x/translate.c index 02bc7058fd..a3992dae5a 100644 --- a/target-s390x/translate.c +++ b/target-s390x/translate.c @@ -5326,10 +5326,9 @@ static ExitStatus translate_one(CPUS390XState *env, DisasContext *s) return ret; } -void gen_intermediate_code(CPUS390XState *env, struct TranslationBlock *tb) +void gen_intermediate_code(CPUState *cpu, struct TranslationBlock *tb) { - S390CPU *cpu = s390_env_get_cpu(env); - CPUState *cs = CPU(cpu); + CPUS390XState *env = cpu->env_ptr; DisasContext dc; target_ulong pc_start; uint64_t next_page_start; @@ -5347,7 +5346,7 @@ void gen_intermediate_code(CPUS390XState *env, struct TranslationBlock *tb) dc.tb = tb; dc.pc = pc_start; dc.cc_op = CC_OP_DYNAMIC; - do_debug = dc.singlestep_enabled = cs->singlestep_enabled; + do_debug = dc.singlestep_enabled = cpu->singlestep_enabled; next_page_start = (pc_start & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE; @@ -5366,7 +5365,7 @@ void gen_intermediate_code(CPUS390XState *env, struct TranslationBlock *tb) tcg_gen_insn_start(dc.pc, dc.cc_op); num_insns++; - if (unlikely(cpu_breakpoint_test(cs, dc.pc, BP_ANY))) { + if (unlikely(cpu_breakpoint_test(cpu, dc.pc, BP_ANY))) { status = EXIT_PC_STALE; do_debug = true; /* The address covered by the breakpoint must be included in @@ -5393,7 +5392,7 @@ void gen_intermediate_code(CPUS390XState *env, struct TranslationBlock *tb) || tcg_op_buf_full() || num_insns >= max_insns || singlestep - || cs->singlestep_enabled)) { + || cpu->singlestep_enabled)) { status = EXIT_PC_STALE; } } while (status == NO_EXIT); @@ -5434,7 +5433,7 @@ void gen_intermediate_code(CPUS390XState *env, struct TranslationBlock *tb) && qemu_log_in_addr_range(pc_start)) { qemu_log_lock(); qemu_log("IN: %s\n", lookup_symbol(pc_start)); - log_target_disas(cs, pc_start, dc.pc - pc_start, 1); + log_target_disas(cpu, pc_start, dc.pc - pc_start, 1); qemu_log("\n"); qemu_log_unlock(); } diff --git a/target-sh4/translate.c b/target-sh4/translate.c index c89a14733f..0c7485d031 100644 --- a/target-sh4/translate.c +++ b/target-sh4/translate.c @@ -1827,10 +1827,9 @@ static void decode_opc(DisasContext * ctx) gen_store_flags(ctx->flags); } -void gen_intermediate_code(CPUSH4State * env, struct TranslationBlock *tb) +void gen_intermediate_code(CPUState *cpu, struct TranslationBlock *tb) { - SuperHCPU *cpu = sh_env_get_cpu(env); - CPUState *cs = CPU(cpu); + CPUSH4State *env = cpu->env_ptr; DisasContext ctx; target_ulong pc_start; int num_insns; @@ -1845,7 +1844,7 @@ void gen_intermediate_code(CPUSH4State * env, struct TranslationBlock *tb) so assume it is a dynamic branch. */ ctx.delayed_pc = -1; /* use delayed pc from env pointer */ ctx.tb = tb; - ctx.singlestep_enabled = cs->singlestep_enabled; + ctx.singlestep_enabled = cpu->singlestep_enabled; ctx.features = env->features; ctx.has_movcal = (ctx.flags & TB_FLAG_PENDING_MOVCA); @@ -1863,7 +1862,7 @@ void gen_intermediate_code(CPUSH4State * env, struct TranslationBlock *tb) tcg_gen_insn_start(ctx.pc, ctx.flags); num_insns++; - if (unlikely(cpu_breakpoint_test(cs, ctx.pc, BP_ANY))) { + if (unlikely(cpu_breakpoint_test(cpu, ctx.pc, BP_ANY))) { /* We have hit a breakpoint - make sure PC is up-to-date */ tcg_gen_movi_i32(cpu_pc, ctx.pc); gen_helper_debug(cpu_env); @@ -1885,7 +1884,7 @@ void gen_intermediate_code(CPUSH4State * env, struct TranslationBlock *tb) ctx.pc += 2; if ((ctx.pc & (TARGET_PAGE_SIZE - 1)) == 0) break; - if (cs->singlestep_enabled) { + if (cpu->singlestep_enabled) { break; } if (num_insns >= max_insns) @@ -1895,7 +1894,7 @@ void gen_intermediate_code(CPUSH4State * env, struct TranslationBlock *tb) } if (tb->cflags & CF_LAST_IO) gen_io_end(); - if (cs->singlestep_enabled) { + if (cpu->singlestep_enabled) { tcg_gen_movi_i32(cpu_pc, ctx.pc); gen_helper_debug(cpu_env); } else { @@ -1929,7 +1928,7 @@ void gen_intermediate_code(CPUSH4State * env, struct TranslationBlock *tb) && qemu_log_in_addr_range(pc_start)) { qemu_log_lock(); qemu_log("IN:\n"); /* , lookup_symbol(pc_start)); */ - log_target_disas(cs, pc_start, ctx.pc - pc_start, 0); + log_target_disas(cpu, pc_start, ctx.pc - pc_start, 0); qemu_log("\n"); qemu_log_unlock(); } diff --git a/target-sparc/translate.c b/target-sparc/translate.c index 2205f89837..6febd91caf 100644 --- a/target-sparc/translate.c +++ b/target-sparc/translate.c @@ -5688,10 +5688,9 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn) } } -void gen_intermediate_code(CPUSPARCState * env, TranslationBlock * tb) +void gen_intermediate_code(CPUState *cpu, TranslationBlock * tb) { - SPARCCPU *cpu = sparc_env_get_cpu(env); - CPUState *cs = CPU(cpu); + CPUSPARCState *env = cpu->env_ptr; target_ulong pc_start, last_pc; DisasContext dc1, *dc = &dc1; int num_insns; @@ -5709,7 +5708,7 @@ void gen_intermediate_code(CPUSPARCState * env, TranslationBlock * tb) dc->def = env->def; dc->fpu_enabled = tb_fpu_enabled(tb->flags); dc->address_mask_32bit = tb_am_enabled(tb->flags); - dc->singlestep = (cs->singlestep_enabled || singlestep); + dc->singlestep = (cpu->singlestep_enabled || singlestep); #ifdef TARGET_SPARC64 dc->fprs_dirty = 0; dc->asi = (tb->flags >> TB_FLAG_ASI_SHIFT) & 0xff; @@ -5735,7 +5734,7 @@ void gen_intermediate_code(CPUSPARCState * env, TranslationBlock * tb) num_insns++; last_pc = dc->pc; - if (unlikely(cpu_breakpoint_test(cs, dc->pc, BP_ANY))) { + if (unlikely(cpu_breakpoint_test(cpu, dc->pc, BP_ANY))) { if (dc->pc != pc_start) { save_state(dc); } @@ -5799,7 +5798,7 @@ void gen_intermediate_code(CPUSPARCState * env, TranslationBlock * tb) qemu_log_lock(); qemu_log("--------------\n"); qemu_log("IN: %s\n", lookup_symbol(pc_start)); - log_target_disas(cs, pc_start, last_pc + 4 - pc_start, 0); + log_target_disas(cpu, pc_start, last_pc + 4 - pc_start, 0); qemu_log("\n"); qemu_log_unlock(); } diff --git a/target-tilegx/translate.c b/target-tilegx/translate.c index 9c734eeba3..4bf7da10e8 100644 --- a/target-tilegx/translate.c +++ b/target-tilegx/translate.c @@ -2370,12 +2370,11 @@ static void translate_one_bundle(DisasContext *dc, uint64_t bundle) } } -void gen_intermediate_code(CPUTLGState *env, struct TranslationBlock *tb) +void gen_intermediate_code(CPUState *cpu, struct TranslationBlock *tb) { - TileGXCPU *cpu = tilegx_env_get_cpu(env); + CPUTLGState *env = cpu->env_ptr; DisasContext ctx; DisasContext *dc = &ctx; - CPUState *cs = CPU(cpu); uint64_t pc_start = tb->pc; uint64_t next_page_start = (pc_start & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE; int num_insns = 0; @@ -2397,7 +2396,7 @@ void gen_intermediate_code(CPUTLGState *env, struct TranslationBlock *tb) if (!max_insns) { max_insns = CF_COUNT_MASK; } - if (cs->singlestep_enabled || singlestep) { + if (cpu->singlestep_enabled || singlestep) { max_insns = 1; } if (max_insns > TCG_MAX_INSNS) { diff --git a/target-tricore/translate.c b/target-tricore/translate.c index 36f734a662..5fb353b8b4 100644 --- a/target-tricore/translate.c +++ b/target-tricore/translate.c @@ -8733,10 +8733,9 @@ static void decode_opc(CPUTriCoreState *env, DisasContext *ctx, int *is_branch) } } -void gen_intermediate_code(CPUTriCoreState *env, struct TranslationBlock *tb) +void gen_intermediate_code(CPUState *cpu, struct TranslationBlock *tb) { - TriCoreCPU *cpu = tricore_env_get_cpu(env); - CPUState *cs = CPU(cpu); + CPUTriCoreState *env = cpu->env_ptr; DisasContext ctx; target_ulong pc_start; int num_insns, max_insns; @@ -8757,7 +8756,7 @@ void gen_intermediate_code(CPUTriCoreState *env, struct TranslationBlock *tb) ctx.pc = pc_start; ctx.saved_pc = -1; ctx.tb = tb; - ctx.singlestep_enabled = cs->singlestep_enabled; + ctx.singlestep_enabled = cpu->singlestep_enabled; ctx.bstate = BS_NONE; ctx.mem_idx = cpu_mmu_index(env, false); @@ -8791,7 +8790,7 @@ void gen_intermediate_code(CPUTriCoreState *env, struct TranslationBlock *tb) && qemu_log_in_addr_range(pc_start)) { qemu_log_lock(); qemu_log("IN: %s\n", lookup_symbol(pc_start)); - log_target_disas(cs, pc_start, ctx.pc - pc_start, 0); + log_target_disas(cpu, pc_start, ctx.pc - pc_start, 0); qemu_log("\n"); qemu_log_unlock(); } diff --git a/target-unicore32/translate.c b/target-unicore32/translate.c index 514d460408..39eaa76b50 100644 --- a/target-unicore32/translate.c +++ b/target-unicore32/translate.c @@ -1869,10 +1869,9 @@ static void disas_uc32_insn(CPUUniCore32State *env, DisasContext *s) } /* generate intermediate code for basic block 'tb'. */ -void gen_intermediate_code(CPUUniCore32State *env, TranslationBlock *tb) +void gen_intermediate_code(CPUState *cpu, TranslationBlock *tb) { - UniCore32CPU *cpu = uc32_env_get_cpu(env); - CPUState *cs = CPU(cpu); + CPUUniCore32State *env = cpu->env_ptr; DisasContext dc1, *dc = &dc1; target_ulong pc_start; uint32_t next_page_start; @@ -1888,7 +1887,7 @@ void gen_intermediate_code(CPUUniCore32State *env, TranslationBlock *tb) dc->is_jmp = DISAS_NEXT; dc->pc = pc_start; - dc->singlestep_enabled = cs->singlestep_enabled; + dc->singlestep_enabled = cpu->singlestep_enabled; dc->condjmp = 0; cpu_F0s = tcg_temp_new_i32(); cpu_F1s = tcg_temp_new_i32(); @@ -1917,7 +1916,7 @@ void gen_intermediate_code(CPUUniCore32State *env, TranslationBlock *tb) tcg_gen_insn_start(dc->pc); num_insns++; - if (unlikely(cpu_breakpoint_test(cs, dc->pc, BP_ANY))) { + if (unlikely(cpu_breakpoint_test(cpu, dc->pc, BP_ANY))) { gen_set_pc_im(dc->pc); gen_exception(EXCP_DEBUG); dc->is_jmp = DISAS_JUMP; @@ -1949,7 +1948,7 @@ void gen_intermediate_code(CPUUniCore32State *env, TranslationBlock *tb) * Also stop translation when a page boundary is reached. This * ensures prefetch aborts occur at the right place. */ } while (!dc->is_jmp && !tcg_op_buf_full() && - !cs->singlestep_enabled && + !cpu->singlestep_enabled && !singlestep && dc->pc < next_page_start && num_insns < max_insns); @@ -1958,7 +1957,7 @@ void gen_intermediate_code(CPUUniCore32State *env, TranslationBlock *tb) if (dc->condjmp) { /* FIXME: This can theoretically happen with self-modifying code. */ - cpu_abort(cs, "IO on conditional branch instruction"); + cpu_abort(cpu, "IO on conditional branch instruction"); } gen_io_end(); } @@ -1966,7 +1965,7 @@ void gen_intermediate_code(CPUUniCore32State *env, TranslationBlock *tb) /* At this stage dc->condjmp will only be set when the skipped instruction was a conditional branch or trap, and the PC has already been written. */ - if (unlikely(cs->singlestep_enabled)) { + if (unlikely(cpu->singlestep_enabled)) { /* Make sure the pc is updated, and raise a debug exception. */ if (dc->condjmp) { if (dc->is_jmp == DISAS_SYSCALL) { @@ -2027,7 +2026,7 @@ done_generating: qemu_log_lock(); qemu_log("----------------\n"); qemu_log("IN: %s\n", lookup_symbol(pc_start)); - log_target_disas(cs, pc_start, dc->pc - pc_start, 0); + log_target_disas(cpu, pc_start, dc->pc - pc_start, 0); qemu_log("\n"); qemu_log_unlock(); } diff --git a/target-xtensa/translate.c b/target-xtensa/translate.c index 0858c296ea..3089c3a77c 100644 --- a/target-xtensa/translate.c +++ b/target-xtensa/translate.c @@ -3036,10 +3036,9 @@ static void gen_ibreak_check(CPUXtensaState *env, DisasContext *dc) } } -void gen_intermediate_code(CPUXtensaState *env, TranslationBlock *tb) +void gen_intermediate_code(CPUState *cpu, TranslationBlock *tb) { - XtensaCPU *cpu = xtensa_env_get_cpu(env); - CPUState *cs = CPU(cpu); + CPUXtensaState *env = cpu->env_ptr; DisasContext dc; int insn_count = 0; int max_insns = tb->cflags & CF_COUNT_MASK; @@ -3055,7 +3054,7 @@ void gen_intermediate_code(CPUXtensaState *env, TranslationBlock *tb) } dc.config = env->config; - dc.singlestep_enabled = cs->singlestep_enabled; + dc.singlestep_enabled = cpu->singlestep_enabled; dc.tb = tb; dc.pc = pc_start; dc.ring = tb->flags & XTENSA_TBFLAG_RING_MASK; @@ -3090,7 +3089,7 @@ void gen_intermediate_code(CPUXtensaState *env, TranslationBlock *tb) ++dc.ccount_delta; - if (unlikely(cpu_breakpoint_test(cs, dc.pc, BP_ANY))) { + if (unlikely(cpu_breakpoint_test(cpu, dc.pc, BP_ANY))) { tcg_gen_movi_i32(cpu_pc, dc.pc); gen_exception(&dc, EXCP_DEBUG); dc.is_jmp = DISAS_UPDATE; @@ -3126,7 +3125,7 @@ void gen_intermediate_code(CPUXtensaState *env, TranslationBlock *tb) if (dc.icount) { tcg_gen_mov_i32(cpu_SR[ICOUNT], dc.next_icount); } - if (cs->singlestep_enabled) { + if (cpu->singlestep_enabled) { tcg_gen_movi_i32(cpu_pc, dc.pc); gen_exception(&dc, EXCP_DEBUG); break; @@ -3158,7 +3157,7 @@ void gen_intermediate_code(CPUXtensaState *env, TranslationBlock *tb) qemu_log_lock(); qemu_log("----------------\n"); qemu_log("IN: %s\n", lookup_symbol(pc_start)); - log_target_disas(cs, pc_start, dc.pc - pc_start, 0); + log_target_disas(cpu, pc_start, dc.pc - pc_start, 0); qemu_log("\n"); qemu_log_unlock(); } diff --git a/translate-all.c b/translate-all.c index 3dd9214904..348047f5f5 100644 --- a/translate-all.c +++ b/translate-all.c @@ -1308,7 +1308,7 @@ TranslationBlock *tb_gen_code(CPUState *cpu, tcg_func_start(&tcg_ctx); tcg_ctx.cpu = ENV_GET_CPU(env); - gen_intermediate_code(env, tb); + gen_intermediate_code(cpu, tb); tcg_ctx.cpu = NULL; trace_translate_block(tb, tb->pc, tb->tc_ptr);