@@ -980,6 +980,10 @@ static const TypeInfo nvme_info = {
.instance_size = sizeof(NvmeCtrl),
.class_init = nvme_class_init,
.instance_init = nvme_instance_init,
+ .interfaces = (InterfaceInfo[]) {
+ { INTERFACE_PCIE_DEVICE },
+ { }
+ },
};
static void nvme_register_types(void)
@@ -701,6 +701,10 @@ static const TypeInfo e1000e_info = {
.instance_size = sizeof(E1000EState),
.class_init = e1000e_class_init,
.instance_init = e1000e_instance_init,
+ .interfaces = (InterfaceInfo[]) {
+ { INTERFACE_PCIE_DEVICE },
+ { }
+ },
};
static void e1000e_register_types(void)
@@ -2726,6 +2726,10 @@ static const TypeInfo vmxnet3_info = {
.instance_size = sizeof(VMXNET3State),
.class_init = vmxnet3_class_init,
.instance_init = vmxnet3_instance_init,
+ .interfaces = (InterfaceInfo[]) {
+ { INTERFACE_PCIE_DEVICE },
+ { }
+ },
};
static void vmxnet3_register_types(void)
@@ -209,6 +209,10 @@ static const TypeInfo ioh3420_info = {
.name = "ioh3420",
.parent = TYPE_PCIE_SLOT,
.class_init = ioh3420_class_init,
+ .interfaces = (InterfaceInfo[]) {
+ { INTERFACE_PCIE_DEVICE },
+ { }
+ },
};
static void ioh3420_register_types(void)
@@ -195,6 +195,10 @@ static const TypeInfo xio3130_downstream_info = {
.name = "xio3130-downstream",
.parent = TYPE_PCIE_SLOT,
.class_init = xio3130_downstream_class_init,
+ .interfaces = (InterfaceInfo[]) {
+ { INTERFACE_PCIE_DEVICE },
+ { }
+ },
};
static void xio3130_downstream_register_types(void)
@@ -167,8 +167,20 @@ static const TypeInfo pci_bus_info = {
.class_init = pci_bus_class_init,
};
+static const TypeInfo pcie_interface_info = {
+ .name = INTERFACE_PCIE_DEVICE,
+ .parent = TYPE_INTERFACE,
+};
+
+static void pcie_bus_class_init(ObjectClass *oc, void *opaque)
+{
+ BusClass *bc = BUS_CLASS(oc);
+ bc->device_type = INTERFACE_PCIE_DEVICE;
+}
+
static const TypeInfo pcie_bus_info = {
.name = TYPE_PCIE_BUS,
+ .class_init = pcie_bus_class_init,
.parent = TYPE_PCI_BUS,
};
@@ -2627,6 +2639,7 @@ static void pci_register_types(void)
{
type_register_static(&pci_bus_info);
type_register_static(&pcie_bus_info);
+ type_register_static(&pcie_interface_info);
type_register_static(&pci_device_type_info);
}
@@ -2538,11 +2538,18 @@ static void megasas_register_types(void)
for (i = 0; i < ARRAY_SIZE(megasas_devices); i++) {
const MegasasInfo *info = &megasas_devices[i];
TypeInfo type_info = {};
+ InterfaceInfo pcie_interfaces[] = {
+ { INTERFACE_PCIE_DEVICE },
+ { },
+ };
type_info.name = info->name;
type_info.parent = TYPE_MEGASAS_BASE;
type_info.class_data = (void *)info;
type_info.class_init = megasas_class_init;
+ if (info->is_express) {
+ type_info.interfaces = pcie_interfaces;
+ }
type_register(&type_info);
}
@@ -1306,6 +1306,7 @@ static const TypeInfo pvscsi_info = {
.class_init = pvscsi_class_init,
.interfaces = (InterfaceInfo[]) {
{ TYPE_HOTPLUG_HANDLER },
+ { INTERFACE_PCIE_DEVICE },
{ }
}
};
@@ -3962,6 +3962,10 @@ static const TypeInfo xhci_info = {
.parent = TYPE_PCI_DEVICE,
.instance_size = sizeof(XHCIState),
.class_init = xhci_class_init,
+ .interfaces = (InterfaceInfo[]) {
+ { INTERFACE_PCIE_DEVICE },
+ { }
+ },
};
static void xhci_register_types(void)
@@ -2983,6 +2983,10 @@ static const TypeInfo vfio_pci_dev_info = {
.class_init = vfio_pci_dev_class_init,
.instance_init = vfio_instance_init,
.instance_finalize = vfio_instance_finalize,
+ .interfaces = (InterfaceInfo[]) {
+ { INTERFACE_PCIE_DEVICE },
+ { }
+ },
};
static void register_vfio_pci_dev_type(void)
@@ -1893,6 +1893,10 @@ static const TypeInfo virtio_pci_info = {
.class_init = virtio_pci_class_init,
.class_size = sizeof(VirtioPCIClass),
.abstract = true,
+ .interfaces = (InterfaceInfo[]) {
+ { INTERFACE_PCIE_DEVICE },
+ { }
+ },
};
/* virtio-blk-pci */
@@ -386,6 +386,9 @@ typedef PCIINTxRoute (*pci_route_irq_fn)(void *opaque, int pin);
#define PCI_BUS_GET_CLASS(obj) OBJECT_GET_CLASS(PCIBusClass, (obj), TYPE_PCI_BUS)
#define TYPE_PCIE_BUS "PCIE"
+/* Interface implemented by devices that can be plugged on PCIE buses */
+#define INTERFACE_PCIE_DEVICE "PCIE-device"
+
bool pci_bus_is_express(PCIBus *bus);
bool pci_bus_is_root(PCIBus *bus);
void pci_bus_new_inplace(PCIBus *bus, size_t bus_size, DeviceState *parent,
The new interface name will be used by TYPE_PCIE_BUS to allow only PCIe devices to be plugged, by setting BusClass::supported_device_type = INTERFACE_PCIE_DEVICE. This patch changes all devices that set is_express=1 or set QEMU_PCI_CAP_EXPRESS directly to implement INTERFACE_PCIE_DEVICE. There are two issues I still want to fix in this patch: * Duplication between PCIDeviceClass::is_express and INTERFACE_PCIE_DEVICE. There are two ways of encoding info about a device class supporting PCIe: PCIDeviceClass::is_express, and INTERFACE_PCIE_DEVICE. This duplication needs to be eliminated. * Differentiating PCIe-only and hybrid devices. There's no obvious way to indicate that a device is supposed to be plugged on PCIe buses only. PCIDeviceClass::is_express and INTERFACE_PCIE_DEVICE only indicate PCIe is supported, but doesn't say anything about legacy PCI being (un)supported. Some PCIe device classes also support legacy PCI, and some don't. Signed-off-by: Eduardo Habkost <ehabkost@redhat.com> --- hw/block/nvme.c | 4 ++++ hw/net/e1000e.c | 4 ++++ hw/net/vmxnet3.c | 4 ++++ hw/pci-bridge/ioh3420.c | 4 ++++ hw/pci-bridge/xio3130_downstream.c | 4 ++++ hw/pci/pci.c | 13 +++++++++++++ hw/scsi/megasas.c | 7 +++++++ hw/scsi/vmw_pvscsi.c | 1 + hw/usb/hcd-xhci.c | 4 ++++ hw/vfio/pci.c | 4 ++++ hw/virtio/virtio-pci.c | 4 ++++ include/hw/pci/pci.h | 3 +++ 12 files changed, 56 insertions(+)