From patchwork Wed Nov 16 20:03:39 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 695830 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3tJx2H5j29z9t0J for ; Thu, 17 Nov 2016 07:39:35 +1100 (AEDT) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="Bqbj2nlG"; dkim-atps=neutral Received: from localhost ([::1]:54741 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1c76zV-0006iY-20 for incoming@patchwork.ozlabs.org; Wed, 16 Nov 2016 15:39:33 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:56120) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1c76RI-0002cl-AB for qemu-devel@nongnu.org; Wed, 16 Nov 2016 15:04:13 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1c76RG-0002fO-Cu for qemu-devel@nongnu.org; Wed, 16 Nov 2016 15:04:12 -0500 Received: from mail-wm0-x243.google.com ([2a00:1450:400c:c09::243]:34808) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1c76RG-0002fA-6N for qemu-devel@nongnu.org; Wed, 16 Nov 2016 15:04:10 -0500 Received: by mail-wm0-x243.google.com with SMTP id g23so14715765wme.1 for ; Wed, 16 Nov 2016 12:04:10 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=sender:from:to:subject:date:message-id:in-reply-to:references; bh=FlqUYt/4GBsqUCZMBr8DVT1UiD2FrF6/vDWJbiPF72c=; b=Bqbj2nlGrHQGvCymByKh8TVQksY60q8eFrunuiuK5h/BamifGD+grY3s5+RgyaJNZN Z37SDmZPS5mo3iEwnxamuixC+Cfmk6ApkaH8y5fd4Uvl+o7wSbMlHwtuv8dWULxirQCa OibSqowA7kaOdmeYMrd8mUIfWkxidOyhAE9nXO2s3l6bNwbvXCaghB+d9vZxrqwjz6rn Btqfz1gIDXZa6Us0LvHlBihctNANQQStDmHOpZL1iahxXoSC1tcUYYoYWDp0NO9aVZJ9 rNcESqSycX4HSzG75mkVp0hlfJfL8dv9WgBzSYekOeGuqJmHzLj1HKWICTefb6n6fSZw 0NVQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:sender:from:to:subject:date:message-id :in-reply-to:references; bh=FlqUYt/4GBsqUCZMBr8DVT1UiD2FrF6/vDWJbiPF72c=; b=iMpJyyDIXPftvHUKSfqWZWwB0vJCSTlOQv+IGNhVgVGgERs5FDH4Adg2UDlqxe/UgY cRQ3U+W8wFh4OcFLa0mXAfkVeJW+Fvazp8Hlm17reHxY5qYT2DNrCPlLQS7Pv99bnFvy HUkzJYhW5TVfcDNctOWcM1mLMinrEWr+pgOHvLLjCj5k1nmjcg3/r5+zXIIdR/zgTEZL zDXZHKhr7pYPHjE0SdzW6nFrBtjS9Fj6Zq1PTqrFtNxsMohlucwa5qeItHFQeIgp9YG9 URDlIS9zTAAGF9zT6XoudUphnIBrc1iELkjBvXEcBe71lOZSvSW63A0QpqmVBEY8yvqT QNNg== X-Gm-Message-State: ABUngvdUokkn+GTelGfei8i76QkJqZnnygcEcEBVOYxu3xikVcikA23eKSfUNowQcpbpSg== X-Received: by 10.28.178.205 with SMTP id b196mr12384866wmf.8.1479326648799; Wed, 16 Nov 2016 12:04:08 -0800 (PST) Received: from bigtime.twiddle.net ([87.111.149.139]) by smtp.gmail.com with ESMTPSA id x188sm3292wmx.4.2016.11.16.12.04.07 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 16 Nov 2016 12:04:08 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 16 Nov 2016 21:03:39 +0100 Message-Id: <1479326625-10682-13-git-send-email-rth@twiddle.net> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1479326625-10682-1-git-send-email-rth@twiddle.net> References: <1479326625-10682-1-git-send-email-rth@twiddle.net> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 2a00:1450:400c:c09::243 Subject: [Qemu-devel] [patch v3 12/18] tcg/s390: Support deposit into zero X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Since we can no longer use matching constraints, this does mean we must handle that data movement by hand. Signed-off-by: Richard Henderson --- tcg/s390/tcg-target.inc.c | 30 ++++++++++++++++++++++++++---- 1 file changed, 26 insertions(+), 4 deletions(-) diff --git a/tcg/s390/tcg-target.inc.c b/tcg/s390/tcg-target.inc.c index 083c992..f4c510e 100644 --- a/tcg/s390/tcg-target.inc.c +++ b/tcg/s390/tcg-target.inc.c @@ -43,6 +43,7 @@ #define TCG_CT_CONST_XORI 0x400 #define TCG_CT_CONST_CMPI 0x800 #define TCG_CT_CONST_ADLI 0x1000 +#define TCG_CT_CONST_ZERO 0x2000 /* Several places within the instruction set 0 means "no register" rather than TCG_REG_R0. */ @@ -404,6 +405,9 @@ static int target_parse_constraint(TCGArgConstraint *ct, const char **pct_str) case 'C': ct->ct |= TCG_CT_CONST_CMPI; break; + case 'Z': + ct->ct |= TCG_CT_CONST_ZERO; + break; default: return -1; } @@ -543,6 +547,8 @@ static int tcg_target_const_match(tcg_target_long val, TCGType type, return tcg_match_xori(type, val); } else if (ct & TCG_CT_CONST_CMPI) { return tcg_match_cmpi(type, val); + } else if (ct & TCG_CT_CONST_ZERO) { + return val == 0; } return 0; @@ -1240,11 +1246,11 @@ static void tgen_movcond(TCGContext *s, TCGType type, TCGCond c, TCGReg dest, } static void tgen_deposit(TCGContext *s, TCGReg dest, TCGReg src, - int ofs, int len) + int ofs, int len, int z) { int lsb = (63 - ofs); int msb = lsb - (len - 1); - tcg_out_risbg(s, dest, src, msb, lsb, ofs, 0); + tcg_out_risbg(s, dest, src, msb, lsb, ofs, z); } static void tgen_extract(TCGContext *s, TCGReg dest, TCGReg src, @@ -2157,8 +2163,24 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, break; OP_32_64(deposit): - tgen_deposit(s, args[0], args[2], args[3], args[4]); + a0 = args[0], a1 = args[1], a2 = args[2]; + if (const_args[1]) { + tgen_deposit(s, a0, a2, args[3], args[4], 1); + } else { + /* Since we can't support "0Z" as a constraint, we allow a1 in + any register. Fix things up as if a matching constraint. */ + if (a0 != a1) { + TCGType type = (opc == INDEX_op_deposit_i64); + if (a0 == a2) { + tcg_out_mov(s, type, TCG_TMP0, a2); + a2 = TCG_TMP0; + } + tcg_out_mov(s, type, a0, a1); + } + tgen_deposit(s, a0, a2, args[3], args[4], 0); + } break; + OP_32_64(extract): tgen_extract(s, args[0], args[1], args[2], args[3]); break; @@ -2230,7 +2252,7 @@ static const TCGTargetOpDef s390_op_defs[] = { { INDEX_op_brcond_i32, { "r", "rC" } }, { INDEX_op_setcond_i32, { "r", "r", "rC" } }, { INDEX_op_movcond_i32, { "r", "r", "rC", "r", "0" } }, - { INDEX_op_deposit_i32, { "r", "0", "r" } }, + { INDEX_op_deposit_i32, { "r", "rZ", "r" } }, { INDEX_op_extract_i32, { "r", "r" } }, { INDEX_op_qemu_ld_i32, { "r", "L" } },