From patchwork Wed Nov 2 21:15:17 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Laurent Vivier X-Patchwork-Id: 690602 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3t8LWz2Zzjz9vDV for ; Thu, 3 Nov 2016 08:17:03 +1100 (AEDT) Received: from localhost ([::1]:57783 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1c22u5-0007Uw-7K for incoming@patchwork.ozlabs.org; Wed, 02 Nov 2016 17:17:01 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:38618) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1c22so-0006X0-7t for qemu-devel@nongnu.org; Wed, 02 Nov 2016 17:15:43 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1c22sj-000490-50 for qemu-devel@nongnu.org; Wed, 02 Nov 2016 17:15:42 -0400 Received: from mout.kundenserver.de ([212.227.17.13]:50126) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1c22si-00048O-SF for qemu-devel@nongnu.org; Wed, 02 Nov 2016 17:15:37 -0400 Received: from Quad.localdomain ([78.238.229.36]) by mrelayeu.kundenserver.de (mreue102) with ESMTPSA (Nemesis) id 0M89Y1-1colgd27FZ-00vjiP; Wed, 02 Nov 2016 22:15:26 +0100 From: Laurent Vivier To: qemu-devel@nongnu.org Date: Wed, 2 Nov 2016 22:15:17 +0100 Message-Id: <1478121319-31986-2-git-send-email-laurent@vivier.eu> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1478121319-31986-1-git-send-email-laurent@vivier.eu> References: <1478121319-31986-1-git-send-email-laurent@vivier.eu> X-Provags-ID: V03:K0:H4oRelijkEASSOCJbPMn/5sKRvE0v/vYl0A5pwGUPjcjBN0AWDR BCs+tmQC0JUjbmO8mRucKR9ArMKhf1Xb3lmcEtY/KrQsvDd+rYJ9YHJW8KICl7tmt2u7ueq wNqz1HVjF7F7wzBKccjgdyNSD6Mu2X/kvbujc6UO24RqyemOnixQ34Xw4sK/+xGKYO1ZNLz 0vR/QahvqNHdHIJ1Jcxow== X-UI-Out-Filterresults: notjunk:1; V01:K0:2Pmc/KE8GiM=:5Q/G6CDSiMZ5/oz8zT7DOn 8Fp9rvDmABjAEna1jiOWHBVYb9Iw2ddQpjpiTP4+xHah9noPl9D144bDc8tD2gf/1/iQ2uNof dfjk5wgDTTt2pjvxdVXBGHQsqFkxokP23e8GinLta+XIOPK0LHnaJyqq5qYRwgFyQAvhRwDmJ d3sedpzdbCT+4sekDu0bwZLDTv+hvBwIXdP4bDY9bCl/eFw30cPT45NQ1cZ+ADVaUmge2us1G BtBQIpcpsIYpUz/ZaMEb4UnP11wCalUV4iaWbSytxrepO/AQ2VJjLafLiIXVaTS1h0/sPCZDn 1P7qqabu1h2YBFFjXKa1jSkIM0qLs+FATytyRhg3A5yX3f5GvjJsVTABC6Abnp0zpXyeYiU3g RenBQRuNECHinLsnLwUajgH25RXnno1LAH7OV+z/F7fq/ijEo8JJLW3etOpMEpTHqQthNjcW8 cOUI6CFe47TGQSeWV6BIHZFUd51S0Kq+mNNRPuoJkYyuFmVz+Eolld6q8dukQ68Z+kwuwsDyK S6oQesIpPPlzGbTZbS13wOj5Po8x5tGukdJhU5dXAkHYSqdEugsPcWi2bScYB3MzVCD+LFbxa AvI3FPS0yZ4rZuldXvFYsu1sAYp9EupeAwuxZnGzVGw3CgYFs4DrlrFW9TGcdZyeZbFVmkQ4q RxcDHjDXus4RLF0q96B2yQVbXeDKdeIiUx57p/ZGQ5gwSgCj3zjuToNLTi/Io32tlz5A= X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 212.227.17.13 Subject: [Qemu-devel] [PATCH v2 1/3] target-m68k: add abcd/sbcd/nbcd X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Laurent Vivier , gerg@uclinux.org, schwab@linux-m68k.org, agraf@suse.de, Richard Henderson Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Laurent Vivier --- target-m68k/translate.c | 242 ++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 242 insertions(+) diff --git a/target-m68k/translate.c b/target-m68k/translate.c index d0a3b0f..1cf88a4 100644 --- a/target-m68k/translate.c +++ b/target-m68k/translate.c @@ -1313,6 +1313,243 @@ DISAS_INSN(divl) set_cc_op(s, CC_OP_FLAGS); } +static void bcd_add(TCGv dest, TCGv src) +{ + TCGv t0, t1; + + /* dest10 = dest10 + src10 + X + * + * t1 = src + * t2 = t1 + 0x066 + * t3 = t2 + dest + X + * t4 = t2 ^ dest ^ X + * t5 = t3 ^ t4 + * t6 = ~t5 & 0x110 + * t7 = (t6 >> 2) | (t6 >> 3) + * return t3 - t7 + */ + + /* t1 = (src + 0x066) + dest + X + * = result with some possible exceding 0x6 + */ + + t0 = tcg_const_i32(0x066); + tcg_gen_add_i32(t0, t0, src); + + t1 = tcg_temp_new(); + tcg_gen_add_i32(t1, t0, dest); + tcg_gen_add_i32(t1, t1, QREG_CC_X); + + /* we will remove exceding 0x6 where there is no carry */ + + /* t0 = (src + 0x0066) ^ dest ^ X + * = t1 without carries + */ + + tcg_gen_xor_i32(t0, t0, dest); + tcg_gen_xor_i32(t0, t0, QREG_CC_X); + + /* extract the carries + * t0 = t0 ^ t1 + * = only the carries + */ + + tcg_gen_xor_i32(t0, t0, t1); + + /* generate 0x1 where there is no carry */ + + tcg_gen_not_i32(t0, t0); + tcg_gen_andi_i32(t0, t0, 0x110); + + /* for each 0x10, generate a 0x6 */ + + tcg_gen_shri_i32(dest, t0, 2); + tcg_gen_shri_i32(t0, t0, 3); + tcg_gen_or_i32(dest, dest, t0); + tcg_temp_free(t0); + + /* remove the exceding 0x6 + * for digits that have not generated a carry + */ + + tcg_gen_sub_i32(dest, t1, dest); + tcg_temp_free(t1); +} + +static void bcd_sub(TCGv dest, TCGv src) +{ + TCGv t0, t1, t2; + + /* dest10 = dest10 - src10 - X + * = bcd_add(dest + 1 - X, 0xf99 - src) + */ + + /* t0 = 0xfff - src */ + + t0 = tcg_temp_new(); + tcg_gen_neg_i32(t0, src); + tcg_gen_addi_i32(t0, t0, 0xfff); + + /* t1 = t0 + dest + 1 - X*/ + + t1 = tcg_temp_new(); + tcg_gen_add_i32(t1, t0, dest); + tcg_gen_addi_i32(t1, t1, 1); + tcg_gen_sub_i32(t1, t1, QREG_CC_X); + + /* t2 = t0 ^ dest ^ 1 ^ X */ + + t2 = tcg_temp_new(); + tcg_gen_xor_i32(t2, t0, dest); + tcg_gen_xori_i32(t2, t2, 1); + tcg_gen_xor_i32(t2, t2, QREG_CC_X); + + /* t0 = t1 ^ t2 */ + + tcg_gen_xor_i32(t0, t1, t2); + + /* t2 = ~t0 & 0x110 */ + + tcg_gen_not_i32(t2, t0); + tcg_gen_andi_i32(t2, t2, 0x110); + + /* t0 = (t2 >> 2) | (t2 >> 3) */ + + tcg_gen_shri_i32(t0, t2, 2); + tcg_gen_shri_i32(t2, t2, 3); + tcg_gen_or_i32(t0, t0, t2); + + /* return t1 - t0 */ + + tcg_gen_sub_i32(dest, t1, t0); +} + +static void bcd_flags(TCGv val) +{ + tcg_gen_andi_i32(QREG_CC_C, val, 0x0ff); + tcg_gen_or_i32(QREG_CC_Z, QREG_CC_Z, QREG_CC_C); + + tcg_gen_movi_i32(QREG_CC_X, 0); + tcg_gen_andi_i32(val, val, 0xf00); + tcg_gen_setcond_i32(TCG_COND_NE, QREG_CC_C, val, QREG_CC_X); + + tcg_gen_mov_i32(QREG_CC_X, QREG_CC_C); +} + +DISAS_INSN(abcd_reg) +{ + TCGv src; + TCGv dest; + + gen_flush_flags(s); /* !Z is sticky */ + + src = gen_extend(DREG(insn, 0), OS_BYTE, 0); + dest = gen_extend(DREG(insn, 9), OS_BYTE, 0); + bcd_add(dest, src); + gen_partset_reg(OS_BYTE, DREG(insn, 9), dest); + + bcd_flags(dest); +} + +DISAS_INSN(abcd_mem) +{ + TCGv src; + TCGv addr_src; + TCGv dest; + TCGv addr_dest; + + gen_flush_flags(s); /* !Z is sticky */ + + addr_src = tcg_temp_new(); + tcg_gen_subi_i32(addr_src, AREG(insn, 0), opsize_bytes(OS_BYTE)); + src = gen_load(s, OS_BYTE, addr_src, 0); + + addr_dest = tcg_temp_new(); + if (REG(insn, 0) == REG(insn, 9)) { + tcg_gen_subi_i32(addr_dest, addr_src, opsize_bytes(OS_BYTE)); + } else { + tcg_gen_subi_i32(addr_dest, AREG(insn, 9), opsize_bytes(OS_BYTE)); + } + dest = gen_load(s, OS_BYTE, addr_dest, 0); + + bcd_add(dest, src); + + gen_store(s, OS_BYTE, addr_dest, dest); + + tcg_gen_mov_i32(AREG(insn, 0), addr_src); + tcg_temp_free(addr_src); + tcg_gen_mov_i32(AREG(insn, 9), addr_dest); + tcg_temp_free(addr_dest); + + bcd_flags(dest); +} + +DISAS_INSN(sbcd_reg) +{ + TCGv src, dest; + + gen_flush_flags(s); /* !Z is sticky */ + + src = gen_extend(DREG(insn, 0), OS_BYTE, 0); + dest = gen_extend(DREG(insn, 9), OS_BYTE, 0); + + bcd_sub(dest, src); + + gen_partset_reg(OS_BYTE, DREG(insn, 9), dest); + + bcd_flags(dest); +} + +DISAS_INSN(sbcd_mem) +{ + TCGv src, dest; + TCGv addr_src, addr_dest; + + gen_flush_flags(s); /* !Z is sticky */ + + addr_src = tcg_temp_new(); + tcg_gen_subi_i32(addr_src, AREG(insn, 0), opsize_bytes(OS_BYTE)); + src = gen_load(s, OS_BYTE, addr_src, 0); + + addr_dest = tcg_temp_new(); + if (REG(insn, 0) == REG(insn, 9)) { + tcg_gen_subi_i32(addr_dest, addr_src, opsize_bytes(OS_BYTE)); + } else { + tcg_gen_subi_i32(addr_dest, AREG(insn, 9), opsize_bytes(OS_BYTE)); + } + dest = gen_load(s, OS_BYTE, addr_dest, 0); + + bcd_sub(dest, src); + + gen_store(s, OS_BYTE, addr_dest, dest); + + tcg_gen_mov_i32(AREG(insn, 0), addr_src); + tcg_temp_free(addr_src); + tcg_gen_mov_i32(AREG(insn, 9), addr_dest); + tcg_temp_free(addr_dest); + + bcd_flags(dest); +} + +DISAS_INSN(nbcd) +{ + TCGv src, dest; + TCGv addr; + + gen_flush_flags(s); /* !Z is sticky */ + + SRC_EA(env, src, OS_BYTE, 0, &addr); + + dest = tcg_const_i32(0); + bcd_sub(dest, src); + + DEST_EA(env, insn, OS_BYTE, dest, &addr); + + bcd_flags(dest); + + tcg_temp_free(dest); +} + DISAS_INSN(addsub) { TCGv reg; @@ -3616,6 +3853,7 @@ void register_m68k_insns (CPUM68KState *env) INSN(not, 4600, ff00, M68000); INSN(undef, 46c0, ffc0, M68000); INSN(move_to_sr, 46c0, ffc0, CF_ISA_A); + INSN(nbcd, 4800, ffc0, M68000); INSN(linkl, 4808, fff8, M68000); BASE(pea, 4840, ffc0); BASE(swap, 4840, fff8); @@ -3667,6 +3905,8 @@ void register_m68k_insns (CPUM68KState *env) INSN(mvzs, 7100, f100, CF_ISA_B); BASE(or, 8000, f000); BASE(divw, 80c0, f0c0); + INSN(sbcd_reg, 8100, f1f8, M68000); + INSN(sbcd_mem, 8108, f1f8, M68000); BASE(addsub, 9000, f000); INSN(undef, 90c0, f0c0, CF_ISA_A); INSN(subx_reg, 9180, f1f8, CF_ISA_A); @@ -3704,6 +3944,8 @@ void register_m68k_insns (CPUM68KState *env) INSN(exg_aa, c148, f1f8, M68000); INSN(exg_da, c188, f1f8, M68000); BASE(mulw, c0c0, f0c0); + INSN(abcd_reg, c100, f1f8, M68000); + INSN(abcd_mem, c108, f1f8, M68000); BASE(addsub, d000, f000); INSN(undef, d0c0, f0c0, CF_ISA_A); INSN(addx_reg, d180, f1f8, CF_ISA_A);