From patchwork Mon Oct 31 14:47:30 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 689394 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3t6yjV3jR1z9t2N for ; Tue, 1 Nov 2016 02:20:30 +1100 (AEDT) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b=wgnQmTqh; dkim-atps=neutral Received: from localhost ([::1]:36273 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1c1ENv-00049M-OT for incoming@patchwork.ozlabs.org; Mon, 31 Oct 2016 11:20:27 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:40565) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1c1DsV-0007XR-G5 for qemu-devel@nongnu.org; Mon, 31 Oct 2016 10:48:00 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1c1DsU-0007A7-Ff for qemu-devel@nongnu.org; Mon, 31 Oct 2016 10:47:59 -0400 Received: from mail-qk0-x243.google.com ([2607:f8b0:400d:c09::243]:33461) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1c1DsU-0007A0-CE for qemu-devel@nongnu.org; Mon, 31 Oct 2016 10:47:58 -0400 Received: by mail-qk0-x243.google.com with SMTP id x190so3205645qkb.0 for ; Mon, 31 Oct 2016 07:47:58 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references; bh=TQZ0M5d7s42Mbc3oxIGKLetJdWxsP6e6BYqiy2we62A=; b=wgnQmTqhcurA0TMAB9mhDr6qWrN4NB3sjObVl0bHOkfYBdpIrQI1uZobqpqnuYmq2y 0WZwsD/HocE2Rvn7qDTeCBl2IN1H4D0iJkdtciknIEH67PLk7hzx25bRzdim2hcFRzw+ Mr5yRFWwJLCvrwG+fvwkLS62Zu7lCyhM7FTzU9aiVdIwcDOBXvV30k97U/G1qRfELmum FpRkrk8+/YB+RrnDSJ5qPf3ljacLkch+xj5BBRlZKJWYqwhMevca2O8wgLeadzJNtb5s mIP3OT7iRxpzVWdyROHW+iQFcmibLHbxKqr8bGSQV/dmnEaPc8pSqkmIudTVhvXkPeOx YLKg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references; bh=TQZ0M5d7s42Mbc3oxIGKLetJdWxsP6e6BYqiy2we62A=; b=LG6a9ASGFxkyaQy652HK6SPX7HaQwJ2z7hKwylQs4QrRIFYOfr+c9EPHJmzrwaeG5Y EzMCdGns3dNKpJ97FTk5WKltCdv9xJVXe91Cmfx34k8D5jEIqS0B6rh1h//DdmSRIhCc HLKbMncmxd+oei3klVoWYtDjpch+ycH69ziEyeJ4erJZHICoEvf/5o8mSjRgSyRnPQD/ VgVhUFAmsB3iUzVHVwy3QHS3ehjPxKdPehRBBr6ZGXvefWw7LTaLJLE/f432yJfXeyIb xxivq/PuY+wH3xpzma5Njc2kb/MB2trpC0RUZyR8v5A1TqeKlwUwSQUl5vRuhVT2Gnq4 SLGg== X-Gm-Message-State: ABUngvcitgdd2MbfAjWHXhRi8EhODfUZJZi2KcmtCfAPMcplmAhWecfFMjiVtqNHMbrNNA== X-Received: by 10.55.109.67 with SMTP id i64mr23163522qkc.321.1477925277745; Mon, 31 Oct 2016 07:47:57 -0700 (PDT) Received: from bigtime.twiddle.net.com ([64.134.26.173]) by smtp.gmail.com with ESMTPSA id k48sm13394449qtc.22.2016.10.31.07.47.56 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 31 Oct 2016 07:47:57 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 31 Oct 2016 08:47:30 -0600 Message-Id: <1477925253-17772-7-git-send-email-rth@twiddle.net> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1477925253-17772-1-git-send-email-rth@twiddle.net> References: <1477925253-17772-1-git-send-email-rth@twiddle.net> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 2607:f8b0:400d:c09::243 Subject: [Qemu-devel] [PULL for-2.8 6/9] target-microblaze: Cleanup dec_mul X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Use tcg_gen_mul_tl for muli and mul instructions. Use tcg_gen_muls2_tl for mulh instruction. Use tcg_gen_mulu2_tl for mulhu instruction. Use tcg_gen_mulsu2_tl for mulhsu instruction. Note that this last fixes a bug, in that mulhsu was previously treating both operands as signed, instead of treating rb as unsigned. Tested-by: Edgar E. Iglesias Reviewed-by: Edgar E. Iglesias Signed-off-by: Richard Henderson Message-Id: <1475011433-24456-3-git-send-email-rth@twiddle.net> --- target-microblaze/translate.c | 61 +++++++------------------------------------ 1 file changed, 9 insertions(+), 52 deletions(-) diff --git a/target-microblaze/translate.c b/target-microblaze/translate.c index 5274191..de2090a 100644 --- a/target-microblaze/translate.c +++ b/target-microblaze/translate.c @@ -581,50 +581,10 @@ static void dec_msr(DisasContext *dc) } } -/* 64-bit signed mul, lower result in d and upper in d2. */ -static void t_gen_muls(TCGv d, TCGv d2, TCGv a, TCGv b) -{ - TCGv_i64 t0, t1; - - t0 = tcg_temp_new_i64(); - t1 = tcg_temp_new_i64(); - - tcg_gen_ext_i32_i64(t0, a); - tcg_gen_ext_i32_i64(t1, b); - tcg_gen_mul_i64(t0, t0, t1); - - tcg_gen_extrl_i64_i32(d, t0); - tcg_gen_shri_i64(t0, t0, 32); - tcg_gen_extrl_i64_i32(d2, t0); - - tcg_temp_free_i64(t0); - tcg_temp_free_i64(t1); -} - -/* 64-bit unsigned muls, lower result in d and upper in d2. */ -static void t_gen_mulu(TCGv d, TCGv d2, TCGv a, TCGv b) -{ - TCGv_i64 t0, t1; - - t0 = tcg_temp_new_i64(); - t1 = tcg_temp_new_i64(); - - tcg_gen_extu_i32_i64(t0, a); - tcg_gen_extu_i32_i64(t1, b); - tcg_gen_mul_i64(t0, t0, t1); - - tcg_gen_extrl_i64_i32(d, t0); - tcg_gen_shri_i64(t0, t0, 32); - tcg_gen_extrl_i64_i32(d2, t0); - - tcg_temp_free_i64(t0); - tcg_temp_free_i64(t1); -} - /* Multiplier unit. */ static void dec_mul(DisasContext *dc) { - TCGv d[2]; + TCGv tmp; unsigned int subcode; if ((dc->tb_flags & MSR_EE_FLAG) @@ -636,13 +596,11 @@ static void dec_mul(DisasContext *dc) } subcode = dc->imm & 3; - d[0] = tcg_temp_new(); - d[1] = tcg_temp_new(); if (dc->type_b) { LOG_DIS("muli r%d r%d %x\n", dc->rd, dc->ra, dc->imm); - t_gen_mulu(cpu_R[dc->rd], d[1], cpu_R[dc->ra], *(dec_alu_op_b(dc))); - goto done; + tcg_gen_mul_tl(cpu_R[dc->rd], cpu_R[dc->ra], *(dec_alu_op_b(dc))); + return; } /* mulh, mulhsu and mulhu are not available if C_USE_HW_MUL is < 2. */ @@ -651,30 +609,29 @@ static void dec_mul(DisasContext *dc) /* nop??? */ } + tmp = tcg_temp_new(); switch (subcode) { case 0: LOG_DIS("mul r%d r%d r%d\n", dc->rd, dc->ra, dc->rb); - t_gen_mulu(cpu_R[dc->rd], d[1], cpu_R[dc->ra], cpu_R[dc->rb]); + tcg_gen_mul_tl(cpu_R[dc->rd], cpu_R[dc->ra], cpu_R[dc->rb]); break; case 1: LOG_DIS("mulh r%d r%d r%d\n", dc->rd, dc->ra, dc->rb); - t_gen_muls(d[0], cpu_R[dc->rd], cpu_R[dc->ra], cpu_R[dc->rb]); + tcg_gen_muls2_tl(tmp, cpu_R[dc->rd], cpu_R[dc->ra], cpu_R[dc->rb]); break; case 2: LOG_DIS("mulhsu r%d r%d r%d\n", dc->rd, dc->ra, dc->rb); - t_gen_muls(d[0], cpu_R[dc->rd], cpu_R[dc->ra], cpu_R[dc->rb]); + tcg_gen_mulsu2_tl(tmp, cpu_R[dc->rd], cpu_R[dc->ra], cpu_R[dc->rb]); break; case 3: LOG_DIS("mulhu r%d r%d r%d\n", dc->rd, dc->ra, dc->rb); - t_gen_mulu(d[0], cpu_R[dc->rd], cpu_R[dc->ra], cpu_R[dc->rb]); + tcg_gen_mulu2_tl(tmp, cpu_R[dc->rd], cpu_R[dc->ra], cpu_R[dc->rb]); break; default: cpu_abort(CPU(dc->cpu), "unknown MUL insn %x\n", subcode); break; } -done: - tcg_temp_free(d[0]); - tcg_temp_free(d[1]); + tcg_temp_free(tmp); } /* Div unit. */