From patchwork Fri Oct 28 14:59:23 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 688470 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3t578V48rPz9snk for ; Sat, 29 Oct 2016 02:34:02 +1100 (AEDT) Received: from localhost ([::1]:49853 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1c09AO-0000qi-2t for incoming@patchwork.ozlabs.org; Fri, 28 Oct 2016 11:34:00 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:52202) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1c08d7-0004Vp-OA for qemu-devel@nongnu.org; Fri, 28 Oct 2016 10:59:39 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1c08d5-0005MB-0B for qemu-devel@nongnu.org; Fri, 28 Oct 2016 10:59:37 -0400 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:47447) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1c08d4-0005K7-OQ for qemu-devel@nongnu.org; Fri, 28 Oct 2016 10:59:34 -0400 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.84_2) (envelope-from ) id 1c08cz-0005m6-65 for qemu-devel@nongnu.org; Fri, 28 Oct 2016 15:59:29 +0100 From: Peter Maydell To: qemu-devel@nongnu.org Date: Fri, 28 Oct 2016 15:59:23 +0100 Message-Id: <1477666764-19403-9-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1477666764-19403-1-git-send-email-peter.maydell@linaro.org> References: <1477666764-19403-1-git-send-email-peter.maydell@linaro.org> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PULL 8/9] hw/arm/spitz: Fix reset handling X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" From: Guenter Roeck Using the CPU reset handler for resets triggered by writing into gpio pins other than GPIO01 is not appropriate and does not work, since the reset triggered by writing into GPIO01 is configurable. Use a separate reset handler for spitz to reset the entire system and not just the CPU. Signed-off-by: Guenter Roeck Message-id: 1477597646-24111-1-git-send-email-linux@roeck-us.net Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- hw/arm/spitz.c | 13 ++++++++++++- 1 file changed, 12 insertions(+), 1 deletion(-) diff --git a/hw/arm/spitz.c b/hw/arm/spitz.c index 41cc2ee..949a15a 100644 --- a/hw/arm/spitz.c +++ b/hw/arm/spitz.c @@ -29,6 +29,7 @@ #include "sysemu/block-backend.h" #include "hw/sysbus.h" #include "exec/address-spaces.h" +#include "sysemu/sysemu.h" #undef REG_FMT #define REG_FMT "0x%02lx" @@ -844,9 +845,18 @@ static void spitz_lcd_hsync_handler(void *opaque, int line, int level) spitz_hsync ^= 1; } +static void spitz_reset(void *opaque, int line, int level) +{ + if (level) { + qemu_system_reset_request(); + } +} + static void spitz_gpio_setup(PXA2xxState *cpu, int slots) { qemu_irq lcd_hsync; + qemu_irq reset; + /* * Bad hack: We toggle the LCD hsync GPIO on every GPIO status * read to satisfy broken guests that poll-wait for hsync. @@ -867,7 +877,8 @@ static void spitz_gpio_setup(PXA2xxState *cpu, int slots) qemu_irq_raise(qdev_get_gpio_in(cpu->gpio, SPITZ_GPIO_BAT_COVER)); /* Handle reset */ - qdev_connect_gpio_out(cpu->gpio, SPITZ_GPIO_ON_RESET, cpu->reset); + reset = qemu_allocate_irq(spitz_reset, cpu, 0); + qdev_connect_gpio_out(cpu->gpio, SPITZ_GPIO_ON_RESET, reset); /* PCMCIA signals: card's IRQ and Card-Detect */ if (slots >= 1)