From patchwork Wed Oct 12 19:50:52 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thomas Hanson X-Patchwork-Id: 681397 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3svPfV6pRbz9sD6 for ; Thu, 13 Oct 2016 06:52:50 +1100 (AEDT) Received: from localhost ([::1]:35460 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1buPa2-0003dw-MV for incoming@patchwork.ozlabs.org; Wed, 12 Oct 2016 15:52:46 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:36524) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1buPYr-0002oV-QS for qemu-devel@nongnu.org; Wed, 12 Oct 2016 15:51:34 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1buPYo-0004dj-PS for qemu-devel@nongnu.org; Wed, 12 Oct 2016 15:51:33 -0400 Received: from g4t3428.houston.hpe.com ([15.241.140.76]:31844) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1buPYo-0004aD-KK for qemu-devel@nongnu.org; Wed, 12 Oct 2016 15:51:30 -0400 Received: from TomH-Z-Workstation.americas.hpqcorp.net (tomh-z-workstation.americas.hpqcorp.net [16.78.178.129]) by g4t3428.houston.hpe.com (Postfix) with ESMTP id 9E49D68; Wed, 12 Oct 2016 19:51:26 +0000 (UTC) From: Thomas Hanson To: qemu-devel@nongnu.org Date: Wed, 12 Oct 2016 13:50:52 -0600 Message-Id: <1476301853-15774-4-git-send-email-thomas.hanson@linaro.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1476301853-15774-1-git-send-email-thomas.hanson@linaro.org> References: <1476301853-15774-1-git-send-email-thomas.hanson@linaro.org> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x X-Received-From: 15.241.140.76 Subject: [Qemu-devel] [PATCH v3 3/4] target-arm: Comments to mark location of pending work for 56 bit addresses X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: grant.likely@hpe.com, peter.maydell@linaro.org, thomas.hanson@linaro.org Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Certain instructions which can not directly load a tagged address value may trigger a corner case when the address size is 56 bits. This is because incrementing or offsetting from the current PC can cause an arithetic roll-over into the tag bits. Per the ARM ARM spec, these cases should also be addressed by cleaning up the tag field. Signed-off-by: Thomas Hanson --- target-arm/translate-a64.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/target-arm/translate-a64.c b/target-arm/translate-a64.c index 8321218..b4a4b72 100644 --- a/target-arm/translate-a64.c +++ b/target-arm/translate-a64.c @@ -1232,6 +1232,9 @@ static inline AArch64DecodeFn *lookup_disas_fn(const AArch64DecodeTable *table, */ static void disas_uncond_b_imm(DisasContext *s, uint32_t insn) { + /*If/when address size is 56 bits, this could overflow into address tag + * byte, and that byte should be fixed per ARM ARM spec. + */ uint64_t addr = s->pc + sextract32(insn, 0, 26) * 4 - 4; if (insn & (1U << 31)) { @@ -1259,6 +1262,9 @@ static void disas_comp_b_imm(DisasContext *s, uint32_t insn) sf = extract32(insn, 31, 1); op = extract32(insn, 24, 1); /* 0: CBZ; 1: CBNZ */ rt = extract32(insn, 0, 5); + /*If/when address size is 56 bits, this could overflow into address tag + * byte, and that byte should be fixed per ARM ARM spec. + */ addr = s->pc + sextract32(insn, 5, 19) * 4 - 4; tcg_cmp = read_cpu_reg(s, rt, sf); @@ -1287,6 +1293,9 @@ static void disas_test_b_imm(DisasContext *s, uint32_t insn) bit_pos = (extract32(insn, 31, 1) << 5) | extract32(insn, 19, 5); op = extract32(insn, 24, 1); /* 0: TBZ; 1: TBNZ */ + /*If/when address size is 56 bits, this could overflow into address tag + * byte, and that byte should be fixed per ARM ARM spec. + */ addr = s->pc + sextract32(insn, 5, 14) * 4 - 4; rt = extract32(insn, 0, 5); @@ -1316,6 +1325,9 @@ static void disas_cond_b_imm(DisasContext *s, uint32_t insn) unallocated_encoding(s); return; } + /*If/when address size is 56 bits, this could overflow into address tag + * byte, and that byte should be fixed per ARM ARM spec. + */ addr = s->pc + sextract32(insn, 5, 19) * 4 - 4; cond = extract32(insn, 0, 4);